Regarding the distribution of memory in LAB2:
The schematic is as follows:
/ * * Virtual memory map: permissions * kernel / user * * 4 gig --------> ------------------------ ------ * | | RW / - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *:. : *:.: *:.: * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | rw /- * | | rw / - * | Physical Memory | RW / - * | | RW / - * Kernbase -----> -------------------------------------------------------------------------------- -------- * | Kernel Virtual Page Table | RW / - PDMAP * VPT, KSTACKTOP -> ------------------- --------- * | Kernel Stack | RW / - KSTKSIZE | * | - - - - - - - - - - - PDMAP * | Invalid Memory | - / - | * ULIM ------> ----------- ------------------ - * | R / O User VPT | R- / R-PDMAP * UVPT ----> ----- ------------------------- * | R / o Pages | R- / R-PDMAP * Upages ----> --- --------------------------- * | r / o envs | R- / R-PDMAP * UTOP, UENVS ----- -> ----------------------------
* UXSTACKTOP - / | User Exception Stack | RW / RW BY2PG * ---------------------------- * | Invalid Memory | - / - BY2PG * USTACKTOP ----> ------------------------------ * | NORMAL USER Stack | RW / RW BY2PG * ---------------------------- * | | * | | * ~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * * * * |...... ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~ | * | | * utext -------> -------------- -------------- * | | 2 * PDMAP * 0 ------------> ----------- ---------------- * / concrete significance:
Direct of kernels and users: ULIM
Note that the user with the kernel is the same as the permissions of the kernel in the UTOP-ULIM. There are some core data structures here. Doing so allows users to read these structures.
It can be seen that we have completed the following layout in i386_vm_init (void):
[Kstacktop-pdmap, kstacktop "kernel stack, part in useless bootstack
[Kernbase, 2 ^ 32 - 1] Physical memory to [0, 2 ^ 32-1]
[Upages, Upages Round (NPage * SizeOf (Struct Page)] User Page to PAGES
[Uenvs, uenvs round (nenv * sizeof (struct env), BY2PG)] User Envs to Envs
The IA-32 structure uses segment-type memory management, and page management is optional.
By segment management converts a virtual address into a linear address (Liner Address). If there is no page management, then this linear address is directly converted to the physical address. Otherwise it is mapped to a physical address.
Turn on the page mapping by setting PG (PAGING) FLAG. Bit 31 of Cr0 (Available IN All IA-32 Processors.
What is done in this trial is that the page mapping mechanism is not opened, and the link address from one kernel (0xF0100000 starts) to a mapping process is completed by setting the segment register (0xF0100000) to a mapping process (like we are The test is made in one. After completing the initialization of the page table, start opening the page mapping mechanism, clear the segment register, so that KernBase X => KernBase X => X does this seem to turn off the address mapping process of the segment mapping mechanism.
About page access:
The structure of the x86 is to determine the access rights of the page by setting the association of the page entry:
Below is a macro definition of access rights defined in /inc/mmu.h:
/ * Page Table / Directory Entry Flags
* THESE is defined by the hardware
* /
#define PTE_P 0x1 / * Present * /
#define PTE_W 0x2 / * Writeable * /
#define PTE_U 0x4 / * user * /
#define PTE_PWT 0x8 / * Write-through * /
#define PTE_PCD 0x10 / * Cache-Disable * /
#define PTE_A 0x20 / * Accessed * /
#define PTE_D 0x40 / * dirty * /
#define PTE_PS 0x80 / * Page Size * /
#define PTE_MBZ 0x180 / * Bits Must Be Zero * /
#define PTE_USER 0XE00 / * BITS for User Processes * /
#define PTE_Flags 0xFFF / * All Flags * /
In this trial, we need to set the bit of PTE_P, PTE_W, PTE_U.
PTE_P: Whether this page exists. Set by operating system or application
PTE_W: 0 represents read-only, 1 represents read and write.
PTE_U: 0 Requires Supervisor Permissions, 1 User Permissions
IF The Processor Is Currently OPERATING AT A CPL OF 0, 1, OR 2, IT IS in Supervisor Mode; IT IS OPERATING AT A CPL OF 3, IT IS in User Mode. When the Processor is in Supervisor Mode, IT CAN Access All Pages; WHEN IN User Mode, IT CAN Access ONLY User-Level Pages. - System Programming Guide
This will be understood why the permissions are set like it is given, and it is understood why Linux only uses the CPL of 0 and 3.
E.g
Permissions: Kernel RW, User None is the PTE_W and PTE_P bits.
And for the following code, you should write this:
//
// Make 'Pages' Point to an Array of Size 'NPage' of 'Struct Page'.
// map this array read-only by the user at upages (ie. Perm = PTE_U | PTE_P)
// permissions:
// - Pages - Kernel RW, User None
// - The Image Mapped At Upages - Kernel R, User R
// Your Code Goes here:
Pages = Alloc (Round (NPage * Sizeof (Struct Page), BY2PG), BY2PG, 1);
Boot_map_segment (PGDir, Pages, Round (NPage * SizeOf (Struct Page), BY2PG), PADDR (PAGES), PTE_W);
Boot_map_segment (PGDir, Upages, Round (NPage * SizeOf (Struct Page), BY2PG), PADDR (PAGES), PTE_U);
