6502 microprocessor

xiaoxiao2021-03-06 14

/ * 6502 Microprocessor is the microprocessor used by FC (Family Computer commonly known as Nintendo Red White), which explains the 6502 processor register organization, addressing method, and instruction set. The original article is English, RockCarry has been translated, in the instruction set, RockCarry feels that the translation is not much necessary, so the original text is retained. Note: Symbol & is $ $ in the original text, indicating a hexadecimal number. * /

6502 microprocessor

The following most information is simply mentioned in "Commodore 64 Programmers Reference Manual" because it is useful in electrical form, and there is no difference between this document and 6502 documentation, after all, they are from 6500 families. . I have made modifications in the necessary places and have added some new content.

In theory, you can use any code you can find to simulate 6510 (C64 processor).

6502 register inside the processor

Almost all operations are carried out in the processor. The register is some special memories inside the processor, which are used to calculate or save the calculation results. The 6502 processor has some of the following registers:

accumulator

The accumulator is the most important register within the microprocessor. People have designed a large number of machine instructions to perform the transfer of memory data to the accumulator, transfer the data in the accumulator to memory, modify the contents of the accumulator, or some other operations directly to the accumulator (not affecting the memory). And the accumulator is also a unique register capable of performing an arithmetic instruction.

X Database & Sql Blog Articles

X The address register is a very useful register. Almost all of the delivery instructions can be used for accumulators, but there are still some instructions that can only be used for the x-index register (they are specifically designed for x-indeached registers). Similarly, people also have a large number of machines, allowing you to transfer memory data to the X-Division register, transfer the data of the X-Division register to memory, modify the contents of the X-Division Register, or perform other pairs of x-indeached registers Direct operation.

Y indeached register

The y-alone register is also a very important register. Although almost all of the transfer instructions are designed for accumulators and x-index registers, there are still some instructions that can only be used for the y-alone register (they are specifically designed for Y-Class registers). People also have a large number of machine instructions, allowing you to transfer memory data to the x-indeached register, transfer the data of the y-based register to memory, modify the contents of the y-based register, or perform other other to y-alone registers Direct operation.

Status register

The status register contains 8 sign bits (flag bits = logo something or there is no thing that happens). This register is changed according to the result of arithmetic and logical operations. The meaning of each bit is described as follows:

Bit No. 7 6 5 4 3 2 1 0 S v B D i z C

Bit 0 - C - carry flag: This bit saves most of the meaningful carry of arithmetic operations. When making subtraction operations, the flag is cleared - when a borrowing is needed, it is set to 1 - when there is no borrow. The carry flag is also used to shift and loop shift operations.

Bit 1 - z - zero sign bit: This flag is set to 1 when the arithmetic or logical operation result is generated zero, and is set to zero when the result is not zero.

Bit 2 - I - Interrupt Sign Bit: This flag is an interrupt allow / disable flag. If it is set to 1, the interrupt is disabled, if it is cleared to zero, interrupts allowed.

Bit 3 - D - Decade Mode Sign Bit: When it is set, the carrier is executed, and the operand is performed as a decimal BCD (Binary Coded Decimal, EG. 0x00-0x99 = 0-99) Code, the calculation result is also a BCD code. Bit 4 - B: This flag is set to 1, and when a software interrupt (BRK instruction) is executed.

Bit 5: Not used, always assumes logic 1.

BIT 6 - V - Overflow flag: When the result generated by the arithmetic operation is too large to be represented by one byte, the V flag is set to 1.

Bit 7 - S - Symbol Sign Bit: When the result is a negative number, it is set 1, which is cleared to zero.

The most commonly used flags are C, Z, V, and S.

Program Counter (PC)

The program counter always saves the address of the machine command currently being executed. The operating system is always running due to the Commodore VIC-20 computer (or on all the computers), so the program counter (PC) is always changing. This change will stop unless a microprocessor is shut down through some means.

Stack pointer (the Stack Pointer)

This register saves the position of the stack of stacks. The stack is the computer language instruction of the computer to save temporary data.

Addressing Modes

The execution of the instruction requires the participation of the operand. How many times can indicate where the processor gets to get the required operand. These different ways are called addressing methods in the computer. The 6502 processor provides 11 addressing methods, as described below:

1) Immediate address method (immediate) This mode is given directly in the machine instruction. In assembly language, use this addressing method by adding "#" in front of the operand. For example, LDA # & 0a - means "put it into Leiqi to load a hexadecimal number & 0a". In the machine language, different addressing methods are specified in different code. Therefore, LDA will be compiled into different machine code, depending on the way of use. In this example, it will be assembled as: & a9 & 0a.

2 & 3) Absolute Add and Zero-Page Absolute In this addressing method, the address of the operand is given. Example. LDA & 31F6 - (assembly language) & ad & 31f6 - (machine code) If the address of the operand is on the zero page, all such addresses are 00, which means only one byte (low address) Byte), the processor automatically recognizes such an address and fill 00 in high byte. Example. LDA & F4 & A5 & F4 Note: Different machine code is obtained after different addressing methods. Note: For the 2-byte address, the low byte is first stored, for example: LDA & 31F6 will be stored in 3 bytes in memory, & AD & F6 & 31. Zero page absolute addressing is also commonly referred to as zero page addressing.

4) Implicit Addressing Mode In this addressing mode, the address of the operand is not directly given. They are implicit in the instructions. Example. TAX - (Content of Acoustics to X Download Register) & AA - (Machine Code)

5) Accumulator In this addressing mode, the object of the instruction is the data in the accumulator, so it is not necessary to directly give the operating number. Example. LSR - Logic Right Move & 4a - (Machine Code) 6 & 7) Indexed and Zero-Page Indexed In this addressing mode, the actual address of the operand is The address given by the address given in the command is formed with the value of the x-index register or the y-index register. Example. LDA & 31F6, Y & D9 & 31F6 LDA & 31F6, X & DD & 31F6 Note: Which indefined register is determined by the instruction operation used. In the al-zero address address Address, the X-DERROUS is not mixed, and many instructions that can be addressed by zero page can only use the X-Die-index register. Example. LDA & 20, X & B5 & 20

8) Indirect) This addressing method can only be used for JMP instructions - jump to a new location. In assembly language, it is specified by incorporated between the operand. The number of operands is the address of the memory cell that is saved. Example. JMP (& 215F) Assumption - BYTE VALUE & 215F & 76 & 2160 & 30 This instruction is obtained from & 2154, & 2160 memory cells to get value & 3076, and then treat them as a jump to the address, that is, jump to & 3076 unit. (Remember that the address is low byte first stored)

9) Pre-Indexed Indirect) In this addressing mode, the address of a zero page is added to the x-index register to form an address in the memory in memory. In assembly language, only brackets are used to specify the time-up addressing used. Example. LDA (& 3e, x) & a1 & 3e hypothesis - BYTE VALUE X-Reg & 05 & 0043 & 15 & 0044 & 24 & 2415 & 6e

This command will be implemented as follows: (i) & 3e X register content = & 3e & 05 = & 0043 (ii) Get address saved in the & 0043, & 0044 two byte units = & 2415 (iii) Get content in & 2415 - That is & 6E, send it into the accumulator.

Note A) When a zero page address is added, the address is wrapped around - that is, the addition of the added and the address of a zero page. For example: FF 2 = 0001, not 0101 you expect. Don't forget this when you simulate this addressing method. B) This addressing method can only use the x-index register.

10) Post-indexed indirect) Give an indirect address in this addressing mode, the content of a zero page address (is a double-byte content), this address plus The content of the Y register forms a real address of the operand. Similarly, in the assembly language, this addressing method is also indicated by parentheses. Example. LDA (& 4C), y Note Brackets only enclose the second part of the instruction because it is part of the address operation. Assumption - BYTE VALUE & 004C & 00 & 004D & 21 Y-Reg. & 05 & 2105 & 6D Then this instruction will perform as follows: (i) get the address from & 4c, & 4d unit, ie & 2100 (ii) to the contents of this address and Y register Plus = & 2105 (111) Sending the contents of the address & 2105 into accumulator - that is, send & 6D to the accumulator Note: You can only use the Y register in this addressing mode. 11) Relevance (Relative) This addressing method is used in the conditional branch transfer instruction. This may also be the most useful way to address it. A one-byte value is added to the program counter (PC), and then the program will then run from this address. The number of this byte is considered a sign of a symbol - that is, if the 7 position is 1, then the number given by the 0-6 position is a negative number; if the 7 position is 0, then this number It is a positive number. This allows the transfer instruction to maximize 127 bytes in both directions. Case number. 7 6 5 4 3 2 1 0 Symbol value no sign value value 1 0 1 0 0 1 1 1 -39 & a value 0 0 1 0 0 1 1 1 39 & 27 instruction example: BEQ & A7 & F0 & A7 this The command will check the zero flag, if set, then the decimal number 39 subtracts from the program counter, and then the program is then executed from there. If the zero flag is not set, the program is executed directly. Note: a) After the transfer command, the program counter points to the start position of the transfer instruction before the branch transfer. When calculating the transfer position, you must calculate this. B) Conditional branch transfer instructions work by checking the relevant bits in the status register. When you are making shift, make sure that these flags are properly set or reset, which is usually implemented by using CMP instructions. C) When you need to jump than 127 bytes, you can use the combination of reverse jump instructions and JMP instructions.

----------------------------------- ----------------------- | | MCS6502 microprocessor instruction set - alphabetical order | ---------- -------------------------------------------------- ---------- | | ADC Add Memory TO Acumulator with carry | and "and" Memory With Accumulator | ASL Shift Left One Bit (Memory or Accumulator) | | BCC Branch On Carry Clear | BCS Branch On Carry Set | BEQ Branch on Result Zero | BIT Test Bits in Memory with Accumulator | BMI Branch on Result Minus | BNE Branch on Result not Zero | BPL Branch on Result Plus | BRK Force Break | BVC Branch on Overflow Clear | BVS Branch on Overflow Set | | CLC Clear Carry Flag | CLD Clear Decimal Mode | CLI Clear interrupt Disable Bit | CLV Clear Overflow Flag | CMP Compare Memory and Accumulator | CPX Compare Memory and Index X | CPY Compare Memory and Index Y | | DEC Decrement Memory by One | DEX Decrement Index X by One | DEY Decrement Index Y by One | | EOR "Exclusive-Or" Memory with Accumulator | | INC Increment Memory by One | INX Increment Index X by One | INY Increment Index Y by One | | JMP jump to new location | -------------------------------------- ------------------------------

-------------------------------------------------- ---------------------- | MCS6502 Microprocessor Instruction Set - Alphabetic Sequence | | ----------------- -------------------------------------------------- ----- | JSR Jump to New Location Saving Return Address | | LDA Load Accumulator with Memory | LDX Load Index X with Memory | LDY Load Index Y with Memory | LSR Shift Right One Bit (Memory or Accumulator) | | NOP No Operation | | ORA "OR"

OR | TXS Transfer Index x To Stack Pointer | TYA TRANSFER INDEX Y To Accumulator | --------------------------------- --------------------------------------- The Following Notation Applies to this summary:

A Accumulator Eor Logical Exclusive OR

X, Y Index Registers froms Transfer from Stack

M Memory Tos Transfer to Stack

P Processor Status Register -> Transfer to

S stack pointer <- Transfer from Trans

/ Change V Logical OR

_ No change PC Program Counter

Add PCH Program Counter HIGH

// logical and pcl program counter Low

- Subtract Oper Operand

# Immediate Addressing Mode

Note: At the top of each table is located in parentheses a reference number (Ref: XX) which directs the user to that Section in the MCS6500 Microcomputer Family Programming Manual in which the instruction is defined and discussed.

ADC Add Memory to Acumulator with carry adc

Operation: a m c -> a, c nzcidv / / / / _ _ / (ref: 2.2.1) ---------------- ---- ---------------- -------- -------- ---------- | Addressing Mode | OP code | no. Bytes | no. Cycles | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -- --------- --------- ------- ---------- | Immediate | ADC # gaum | 69 | 2 | 2 | | Zero Page | ADC Oper | 65 | 2 | 3 | | Zero Page, X | ADC Oper, X | 75 | 2 | 4 | | Absolute | ADC Oper | 60 | 3 | 4 | | Absolute, X | ADC OPER, X | 70 | 3 | 4 * | | Absolute, Y | ADC Oper, Y | 79 | 3 | 4 * | | (Indirect, X) | ADC (Oper, X) | 61 | 2 | 6 | | (Indirect), Y | ADC (Oper), Y | 71 | 2 | 5 * | ---------------- ----------------------------- - --------- ---------- * Add 1 if page boundary is crossed.and "and" Memory with Accumulator and

Operation: a // m -> a nzcidv / / _ _ _ _ (ref: 2.2.3.0) -------------- --------- -------------- --------- ------- -------- | Addressing Mode | Assembly | no. Bytes | no. Cycles | --------------------------------- ------ --------- ------- ---------- | Immediate | And #oper | 29 | 2 | 2 | | ZERO Page | And Oper | 25 | 2 | 3 | | Zero Page, X | And Oper, X | 35 | 2 | 4 | | Absolute | And Oper | 2D | 3 | 4 | | Absolute, x | And Oper , X | 3D | 3 | 4 * | | Absolute, Y | And Oper, Y | 39 | 3 | 4 * | | (Indirect, x) | And (Oper, X) | 21 | 2 | 6 | | (Indirect) Y) | And (Oper), Y | 31 | 2 | 5 | ---------------- ----------------------------- - --------- ---------- * Add 1 if page boundary is crossed.

ASL ASL SHIFT Left One Bit (Memory or Accumulator) ASL - - - - Operation: C <- | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | <- 0 - - - - NZCIDV / / / _ _ _ (Ref: 10.2) -------------------------------------------------- ---------------------------- ----- ----- | Addressing Mode | Assembly Language Form | OP Code | NO. Bytes | No. Cycles | ---------------- ----- ---------------- --------- ------- ---------- | Accumulator | ASL A | 0A | 1 | 2 | | Zero Page | ASL Oper | 06 | 2 | 5 | | Zero Page, X | ASL OPER, X | 16 | 2 | 6 | | Absolute | ASL Oper | 0e | 3 | 6 | | Absolute, X | ASL Oper, X | 1e | 3 | 7 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- -------- -

BCC BCC Branch On Carry Clear BCC NZCIDV Operation: branch on c = 0 _ _ _ _ _ _ (Ref: 4.1.1.3) ---------------- -- ------------------- ------- ---------------------- | Addressing Mode | ASSEMBLY LANGUAGE FORM | OP CODE | NO. BYTES | NO. CYCLES | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------- --------- --------- -------- | Relative | BCC Oper | 90 | 2 | 2 * | ---------------- --------------------- - ------- --------- ---------- * Add 1 if branch occurs to same page. * Add 2 if Branch Occurs to Different Page.bcs BCS Branch On Carry Set BCS

Operation: branch on c = 1 nzCIDV _ _ _ _ _ _ _ _ _ (Ref: 4.1.1.4) -------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- --------- -------- | Relative | BCS Oper | B0 | 2 | 2 * | ---------------- --------------------- --------- --------- ---------- * Add 1 if branch occurs to same. * Add 2 if branch occurs to next page.

BEQ Branch on Result Zero Beq Nzcidv Operation: branch on z = 1 _ _ _ _ _ _ (Ref: 4.1.1.5) ---------------- -- ------------------- ------- ---------------------- | Addressing Mode | ASSEMBLY LANGUAGE FORM | OP CODE | NO. BYTES | NO. CYCLES | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------- --------- ------- ---------- | Relative | BEQ Oper | F0 | 2 | 2 * | ---------------- --------------------- - ------ --------- ---------- * Add 1 if branch occurs to same page. * Add 2 if branch occurs to next page.bit Bit Test Bits in Memory with Accumulator Bit

Operation: a //m, m7 -> n, m6 -> v

Bit 6 and 7 Are Transferred to The Status Register. Nzcidv if The result of a // m is Zero kiln z = 1, OtherWise M7 / _ _ _ m6 z = 0 (Ref: 4.2.1.1) ----- ----------- ------------------------------- ---- ----- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ------------- - ---------------------- --------- --------- - -------- | Zero Page | Bit Oper | 24 | 2 | 3 | | Absolute | Bit Oper | 2C | 3 | 4 | --------------- - ---------------------- ------------------- ---- ------

BMI BMI Branch On Result Minus BMI

Operation: branch on n = 1 nzCIDV _ _ _ _ _ _ _ _ (REF: 4.1.1.1) ------------- ----------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- ------- ---------- | Relative | BMI Oper | 30 | 2 | 2 * | ---------------- --------------------- --------- ------- ---------- * Add 1 if branch ivcurs to same page. * Add 1 if branch occurs to diffurs page.bne BRANCH RESULT NOT ZERO BNE

Operation: branch on z = 0 nzcidv _ _ _ _ _ _ _ (ref: 4.1.1.6) -------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- --------- ---------- | Relative | BMI Oper | D0 | 2 | 2 * | ---------------- --------------------- --------- --------- ---------- * Add 1 if branch occurs to same page. * Add 2 if branch occurs to different page.

BPL BPL Branch on Result Plus BPL

Operation: branch on n = 0 NZCIDV _ _ _ _ _ _ (REF: 4.1.1.2) -------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- --------- ---------- | Relative | BPL OPER | 10 | 2 | 2 * | ---------------- --------------------- --------- ------- ---------- * Add 1 if branch occurs to same page. * Add 2 if Branch Occurs to Different Page.Brk Brk Force BREAK BRK

Operation: Forced Interrupt PC 2 TOS P TOS NZCIDV___ 1 _ _ (Ref: 9.11) -------------------------- ------------- --------- ------- ---------- | Addressing Mode | Assembly LANGUAGE FORM | OP CODE | NO. BYTES | NO. CYCLES | ---------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----- --------- ------- -------- | Implied | BRK | 00 | 1 | 7 | - --------------- --------------------- ------- --------- ---------- 1. A brk command cannot be masked by setting I.

BVC BVC Branch On Overflow Clear BVC

Operation: branch on v = 0 nzCIDV _ _ _ _ _ _ _ _ (Ref: 4.1.1.8) -------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- ------- --------- -------- | Relative | BVC Oper | 50 | 2 | 2 * | ---------------- --------------------- --------- --------- -------- * Add 1 if branch occurs to same page. * Add 2 if branch occurs to difference page.bvs bvs branch on overflow set bvs

Operation: branch on v = 1 nzCIDV _ _ _ _ _ _ _ (Ref: 4.1.1.7) -------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- --------- -------- | Relative | BVS Oper | 70 | 2 | 2 * | ---------------- --------------------- --------- --------- ---------- * Add 1 if branch occurs to same page. * Add 2 if branch occurs to different page.

CLC CLC Clear Carry Flag CLC

Operation: 0 -> c nzcidv _ _ 0 _ _ _ (Ref: 3.0.2) ---------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- -------- | Implied | CLC | 18 | 1 | 2 | --- ------------- ----------------------- ------- ------- ---------- CLD CLD Clear Decimal Mode CLD

Operation: 0 -> D Nacidv _ _ _ _ 0 _ (REF: 3.3.2) ------------------------------------------------------------------------ ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- -------- | Implied | CLD | D8 | 1 | 2 | --- ------------- ----------------------- ------- ------- ----------

CLI CLI CLIAR Interrupt Disable Bit CLI

Operation: 0 -> i nzcidv _ _ _ 0 _ _ (ref: 3.2.2) -------------- ------------ ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Implied | CLI | 58 | 1 | 2 | --- ------------- ----------------------- ------- ------- ---------- CLV CLV Clear overflow Flag CLV

Operation: 0 -> v NzCIDV _ _ _ _ _ _ 0 (Ref: 3.6.1) ---------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Implied | CLV | B8 | 1 | 2 | --- ------------- ----------------------- ------- ------- ----------

CMP CMP Compare Memory and Accumulator CMP

Operation: a - m NzCIDV / / / / _ _ _ (Ref: 4.2.1) ----------------------------- ---------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | Op code | no. Cycles | ---------------- ------------------- - --------- --------- ---------- | Immediate | CMP # gaum | C9 | 2 | | Zero Page | CMP OPER | C5 | 2 | 3 | | Zero Page, X | CMP Oper, X | D5 | 2 | 4 | | Absolute | CMP Oper | CD | 3 | 4 | | Absolute, X | CMP Oper, X | DD | 3 | 4 * | | ABSOLUTE, Y | CMP Oper, Y | D9 | 3 | 4 * | | (Indirect, X) | CMP (Oper, X) | C1 | 2 | 6 | | (Indirect), Y | CMP (OPER), Y | D1 | 2 | 5 * | ---------------- ----------------------------- - --------- ---------- * Add 1 if page boundary is crossed.

CPX CPX Compare Memory and INDEX X CPX NZCIDV Operation: x - m / / / _ _ _ (Ref: 7.8) ----------------------- ---------------- --------- ------- ---------- | Addressing Mode | ip code | no. Bytes | no. Cycles | ------------------------------- -------- --------- --------- -------- | Immediate | CPX * Oper | E0 | 2 | 2 | | ZERO PAGE | CPX Oper | E4 | 2 | 3 | | Absolute | CPX Oper | EC | 3 | 4 | ---------------- ---- ------------------- ------- ---------------------- CPY CPY COMPARE MEMORY AND INDEX Y CPY NZCIDV Operation: y - m / / / _ _ _ _ (REF: 7.9) ---------------- --------------------- - ------ --------- ---------- | Addressing Mode | Assembly | NO. BYtes | No. Cycles | - -------------- --------------------- ------- - -------- ---------- | Immediate | CPY * Oper | C0 | 2 | 2 | | ZERO Page | CPY Oper | C4 | 2 | 3 | | Absolute | CPY Oper | CC | 3 | 4 | --------------------------------------- --------- ------- --------

Dec Decrement MEMORY BY DECOPERATION: M - 1 -> M NZCIDV / / _ _ _ _ (Ref: 10.7) ---------------- ---- ---------------- -------- -------- ---------- | Addressing Mode | OP code | no. Bytes | no. Cycles | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -- --------- --------- -------- ---------- | ZERO PAGE | DEC OPER | C6 | 2 | 5 | | ZERO PAGE, X | DEC OPER, X | D6 | 2 | 6 | | Absolute | Dec Oper | CE | 3 | 6 | | Absolute, X | Dec Oper, X | DE | 3 | 7 | ---------------- --------------------- --------- ------- --------

DEX DEX DECREMENT INDEX X by One DEX

Operation: x - 1 -> x NzCIDV / / _ _ _ _ (Ref: 7.6) ---------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --- --------- --------- ---------- | Implied | DEX | CA | 1 | 2 | --- ------------- ----------------------- ------- ------- ----------

Dey Dey Decreystem Index Y by One Dey

Operation: x - 1 -> y NzCIDV / / _ _ _ _ (Ref: 7.7) ---------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | Dey | 88 | 1 | 2 | --- ------------- ----------------------- ------- ------- ---------- EOR ERY "Exclusive-or" Memory with Accumulator EOR

Operation: a EOR M -> a nzcidv / / _ _ _ _ (ref: 2.2.3.2) -------------- ---------- ------------- --------- ------- ---------- | Addressing Mode | Assembly LANGUAGE FORM | OP CODE | NO. BYTES | NO. CYCLES | ---------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----- ------- --------- ---------- | Immediate | EOR # gaple | 49 | 2 | 2 | | Zero Page | EOR OPER | 45 | 2 | 3 | | Zero Page, X | Eor Oper, X | 55 | 2 | 4 | | Absolute | EOR OPER | 40 | 3 | 4 | | Absolute, X | EOR OPER, X | 50 | 3 | 4 * | | ABSOLUTE, Y | EOR OPER, Y | 59 | 3 | 4 * | | (Indirect, x) | EOR (Oper, X) | 41 | 2 | 6 | | (Indirect) Y | EOR (Oper), Y | 51 | 2 | 5 * | ---------------- ----------------------------- - --------- ---------- * Add 1 if page boundary is crossed.

INC Inc.Nzcidv Operation: M 1 -> M / / _ _ _ _ (Ref: 10.6) -------------- ----- --------------------------- -------- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ----------------------------- ------------ ---------- --------- -------- ---------- | Zero Page | Inc Oper | E6 | 2 | 5 | | ZERO PAGE, X | Inc Oper, X | F6 | 2 | 6 | | Absolute | Inc Oper | EE | 3 | 6 | | Absolute, X | Inc Oper, x | Fe | 3 | 7 | ---------------- ---------------------- -------- - --------- ---------- Inx Inx increment index x by one inx nzcidv Operati ON: X 1 -> X / / _ _ _ (Ref: 7.4) ------------------------------- ---------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | Op code | no. Cycles | ---------------- ------------------- - --------- --------- -------- | Implied | Inx | E8 | 1 | 2 | ---- ------------ ----------------------- ------- --- ------ ----------

INY INY INCREMENT INDEX Y One Iny

Operation: x 1 -> x NzCIDV / / _ _ _ _ (Ref: 7.5) -------------------------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Implied | iny | c8 | 1 | 2 | --- ------------- ----------------------- ------- ------- ---------- JMP JMP Jump to New Location JMP

Operation: (PC 1) -> PCL NZCIDV (PC 2) -> PCH (ref: 4.0.2) _ _ _ _ _ _ (REF: 9.8.1) ---------- ------ ------------------------------- --------- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ---------------- - --------------------------------------- --- | Absolute | JMP Oper | 4C | 3 | 3 | | Indirect | JMP (Oper) | 6C | 3 | 5 | ---------------- - -------------------- -------- --------- -------- -

JSR JSR Jump To New Location Saving Return Address JSR

Operation: PC 2 TOS, (PC 1) -> PCL NZCIDV (PC 2) -> PCH_ _ _ _ _ _ (Ref: 8.1) -------------- - ---------------------- --------- ------- - ------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ---------------- --- --------------------------- -------- ---------- | Absolute | JSR Oper | 20 | 3 | 6 | ------------------------------------ --- --------- ------- -------- LDA LDA LOAD Acumulator with memory lda

Operation: m -> a nzcidv / / _ _ _ _ (ref: 2.1.1) -------------- ------------ ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Immediate | LDA # gam | A9 | 2 | | ZERO Page | LDA Oper | A5 | 2 | 3 | | Zero Page, X | LDA Oper, X | B5 | 2 | 4 | | Absolute | LDA Oper | AD | 3 | 4 | | Absolute, X | LDA Oper, x | BD | 3 | 4 * | | Absolute, Y | LDA Oper, Y | B9 | 3 | 4 * | | (Indirect, X) | LDA (Oper, X) | A1 | 2 | 6 | | (Indirect), Y | LDA (OPER), Y | B1 | 2 | 5 * | ---------------- ----------------------------- - --------- ---------- * Add 1 if Page Boundary is crossed.ldx LDX Load Index X with memory ldx

Operation: M -> x NzCIDV / / _ _ _ _ (Ref: 7.0) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Immediate | LDX # gamed | A2 | 2 | | ZERO Page | LDX Oper | A6 | 2 | 3 | | ZERO PAGE, Y | LDX Oper, Y | B6 | 2 | 4 | | Absolute | LDX Oper | AE | 3 | 4 | | Absolute, Y | LDX Oper, Y | BE | 3 | 4 * | --------------------------------------- - ------ --------- ---------- * Add 1 when page boundary is cross.

LDY LDY LOAD INDEX Y with MEMORY LDY NZCIDV Operation: M -> Y / / _ _ __ (Ref: 7.1) ---------------- ---- ---------------- -------- -------- ---------- | Addressing Mode | OP code | no. Bytes | no. Cycles | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -- --------- --------- -------- ---------- | Immediate | LDY # gaine | A0 | 2 | 2 | | ZERO Page | LDY OPER | A4 | 2 | 3 | | Zero Page, X | LDY Oper, X | B4 | 2 | 4 | | Absolute | LDY Oper | AC | 3 | 4 | | Absolute, X | LDY OPER, X | BC | 3 | 4 * | ----------------------------------- ---- --------- ------- -------- * Add 1 when page boundary is crossed.lsr lsr shift right one BI Memory or Accumulator LSR

- - - Operation: 0 -> | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -> C NZCIDV - - - - 0 / / _ _ _ (Ref: 10.1) --------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- ------- -------- | Accumulator | LSR A | 4A | 1 | 2 | | Zero Page | LSR Oper | 46 | 2 | 5 | | Zero Page, X | LSR Oper, X | 56 | 2 | 6 | | Absolute | LSR Oper | 4e | 3 | 6 | | Absolute, X | LSR Oper, x | 5E | 3 | 7 | ---------------- ---------------------- - ------- -------- ---------- NOP NOP No Operation NOP N Z c i d v Operation: no operation (2 cycles) _ _ _ _ _ _ _

---------------- ---------------------- -------- - --------- ---------- | Addressing Mode | Assembly Language Form | OP code | no. Bytes | no. Cycles | ------- --------- ---------------------- ---------- ------ - ---------- | Implied | NOP | EA | 1 | 2 | ---------------- ------ ---------------- -------- -------- ----------

ORA ORA "OR" Memory with Accumulator OraOperation: AVM -> a NzCIDV / / _ _ _ (Ref: 2.2.3.1) ---------------- -- ------------------- ------- ---------------------- | Addressing Mode | ASSEMBLY LANGUAGE FORM | OP CODE | NO. BYTES | NO. CYCLES | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------- --------- --------- -------- | Immediate | ORA # gaMed | 09 | 2 | 2 | | Zero Page | ORA | 05 | 2 | 3 | | Zero Page, X | Ora Oper, X | 15 | 2 | 4 | | Absolute | ORA OPER | 0D | 3 | 4 | | Absolute , X | ORA OPER, X | 10 | 3 | 4 * | | Absolute, Y | Ora Oper, Y | 19 | 3 | 4 * | | (Indirect, X) | ORA (OPER, X) | 01 | 2 | 6 | (Indirect), Y | ORA (Oper), Y | 11 | 2 | 5 | ---------------- ---------- ----------- --------- ------- -------- * Add 1 on Page Crossing

Pha Pha Push Accumulator on Stack PHA

Operation: a TOS NZCIDV____ _ _ (Ref: 8.5) -------------- ---------------- ------- -------- --------- ---------- | Addressing Mode | Assembly | OP Code | No. Bytes | No. Cycles | --------------------------------------- --------- --------- ---------- | Implied | PHA | 48 | 1 | 3 | ------- --------- ---------------------- ---------- ------ --- -------- PHP PHP Push Processor Status on Stack PHP

Operation: P TOS NZCIDV____ _ _ (Ref: 8.11) -------------------------------------------------------------------------------------------------------------------------- ------- -------- --------- ---------- | Addressing Mode | Assembly | OP Code | No. Bytes | No. Cycles | --------------------------------------- --------- --------- -------- | Implied | PHP | 08 | 1 | 3 | ------- --------- ---------------------- ---------- ------ --- ----------

Pla Pla Pull Accumulator from Stack Pla

Operation: a froms nzcidv _ _ _ _ _ _ (Ref: 8.6) -------------------------------- ------- -------- --------- ---------- | Addressing Mode | Assembly | OP Code | No. Bytes | No. Cycles | --------------------------------------- --------- --------- ---------- | Implied | PLA | 68 | 1 | 4 | ------- --------- ---------------------- ---------- ------ - ---------- PLP PLP Pull Processor Status from Stack PLA

Operation: p froms nzcidv from Stack (Ref: 8.12) ------------------------------------ - --------- --------- ---------- | Addressing Mode | Assembly Language Form | OP Code | No. Bytes | No. Cycles | -------------------------------------- ---- ----- --------- -------- | Implied | PLP | 28 | 1 | 4 | ----------- ----- ---------------------- ---------- --------- ----------

ROL ROL ROTATE One Bit Left (Memory or Accumulator) ROL

-------------------------- | m or a | | - - - - - | Operation: - <| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | <- | C | <- NZCIDV - - - - / / / _ _ (Ref: 10.3) --------------- --------- ------------ --------- ------- -------- | Addressing Mode | Assembly Language Form | op code | no. Bytes | ---------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---- --------- ------- -------- | Accumulator | ROL A | 2A | 1 | 2 | Zero Page | ROL OPER | 26 | 2 | 5 | | Zero Page, X | ROL Oper, X | 36 | 2 | 6 | | Absolute | ROL Oper | 2e | 3 | 6 | | Absolute, X | ROL Oper, x | 3E | 3 | 7 | ---------------- --------------------- - ------- -------- ---------- ROR ROUR ROTA TE One Bit Right (Memory or Accumulator) ROR

---------------------------- | | | - - - - | Operation: -> | c | -> | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |> - NZCIDV - - - - - - / / / _ _ _ (ref: 10.4) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Accumulator | ROR A | 6A | 1 | 2 | Zero Page | ROR Oper | 66 | 2 | 5 | | ZERO PAGE, X | ROR OPER, X | 76 | 2 | 6 | | Absolute | ROR OPER | 6E | 3 | 6 | | Absolute, X | ROR OPER, X | 7E | 3 | 7 | ------------------------------------- ---- --------- -------- Note: ROR INSTRUCTION IS Available On MCS650X Microprocessors After June, 1976.

RTI RTI RTURN from Interrupt RTI NZCIDV Operation: P froms PC froms from Stack (Ref: 9.6) ---------------------------------------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Implied | rti | 4D | 1 | 6 | --- ------------- ----------------------- ------- ------- ---------- RTS RTS RTURN from Subroutine RTS NZCIDV Operation: PC froms, PC 1 -> PC _ _ _ _ _ (Ref: 8.2) - --------------- --------------------- ------- --------- ---------- | Addressing Mode | Assembly Language Form | OP CO DE | NO. BYTES | NO. CYCLES | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | RTS | 60 | 1 | 6 | ----- ----------- ------------------------------- ---- ----- ----------

SBC SBC Subtract Memory from Accumulator with Borrow SBC - Operation: A - M - C -> A NzCIDV - / / / / _ _ / Note: C = Borrow (Ref: 2.2.2) --------- ------- --------------------------------- ------ - ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ---------------- ---------------------- ------------------------------------ ------ ---- | Immediate | SBC # gam | E9 | 2 | 2 | | Zero Page | SBC Oper | E5 | 2 | 3 | | Zero Page, X | SBC Oper, X | F5 | 2 | | | Absolute | SBC Oper | ED | 3 | 4 | | Absolute, X | SBC Oper, X | FD | 3 | 4 * | | Absolute, Y | SBC Oper, Y | F9 | 3 | 4 * | | (Indirect, X) | SBC (Oper, X) | E1 | 2 | 6 | | (Indirect), Y | SBC (Oper), Y | F1 | 2 | 5 | ---------------- ----- ---------------- --------- ------- -------- * Add 1 WHEN Page Boundary Is Cross.sec Sec SET Carry Flag Sec

Operation: 1 -> c nzcidv _ _ 1 _ _ _ (Ref: 3.0.1) ---------------------------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Implied | sec | 38 | 1 | 2 | --- ------------- ----------------------- ------- ------- ---------- SED SED SET DECIMAL MODE SED NZCIDV OPERATION: 1 -> D _ _ _ _ 1 _ (Ref: 3.3.1) ---- ------------ ----------------------- ------- --- ------ ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ------------ ---- ---------------------- ---- ----- --------- ---------- | Implied | SED | F8 | 1 | 2 | ----------- ----- ---------------------- ---------- --------- ----------

SEI SEI SET INTERRUPT Disable Status SED NZCIDV Operation: 1 -> i _ _ _ 1 _ _ (Ref: 3.2.1) ---------------- --- --------------------------- -------- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ----------------------------- ------------ ---------- --------- -------- ---------- | Implied | SEI | 78 | 1 | 2 | ---------------- --------------------- --- ---- --------- -------- Sta Store Accumulator in Memory Sta

Operation: a -> m nzcidv _ _ _ _ _ _ _ (ref: 2.1.2) -------------- ---------- ----------- ---------- -------- ---------- | Addressing Mode | Assembly Language Form OP code | no. Bytes | no. Cycles | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- ------- ---------- | Zero Page | Sta Oper | 85 | 2 | 3 | ZERO Page, X | Sta Oper, X | 95 | 2 | 4 | | Absolute | Sta Oper | 80 | 3 | 4 | | Absolute, X | Sta Oper, X | 90 | 3 | 5 | | Absolute, Y | Sta Oper , Y | 99 | 3 | 5 | | (Indirect, X) | STA (Oper, X) | 81 | 2 | 6 | | (Indirect), Y | STA (Oper), Y | 91 | 2 | 6 | ---------------- --------------------- --------- ------- -------- Stx StX Store INDEX X in Memory Stx

Operation: x -> m nzcidv _ _ _ _ _ _ (Ref: 7.2) -------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Zero Page | StX Oper | 86 | 2 | 3 | | ZERO PAGE, Y | Stx Oper, Y | 96 | 2 | 4 | | Absolute | Stx Oper | 8e | 3 | 4 | ---------------- ----- ---------------- --------- ------- ---------- STY STY Store INDEX Y in Memory Sty

Operation: y -> m nzcidv _ _ _ _ _ _ (Ref: 7.3) -------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- -------- | Zero Page | Sty Oper | 84 | 2 | 3 | Zero Page, X | STY OPER, X | 94 | 2 | 4 | | Absolute | Sty Oper | 8C | 3 | 4 | ---------------- ------- ---------------- --------- ------- ----------

Tax Tax Transfer Accumulator To Index X Tax

Operation: a -> x nzcidv / / _ _ _ _ (ref: 7.11) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | TAX | AA | 1 | 2 | ----- ----------- ------------------------------- ---- ----- ---------- Tay Tay Transfer Accumulator To Index Y Tay

Operation: a-> y NzCIDV / / _ _ _ (Ref: 7.13) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | TAY | A8 | 1 | 2 | ----- ----------- ------------------------------- ---- ----- ----------

TSX TSX Transfer Stack PoinTo Index X TSX

Operation: s -> x nzcidv / / _ _ _ _ (ref: 8.9) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | TSX | Ba | 1 | 2 | ----- ----------- ------------------------------- ---- ----- ---------- TXA TXA TRANSFER INDEX X to Accumulator TXA NZCIDV Operation: X -> A / / _ _ _ (Ref: 7.12) -------- ---------- -------------------------------- ----- ---- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ------------------------------------------------------------ - ----------------------------- ---- ------- -------- | Implied | TXA | 8A | 1 | 2 | ------------ ---- ---------------------- ------- ----------- - ---------

TXS TXS TRANSFER INDEX X to Stack Pointer TXS NZCIDV Operation: X -> S _ _ _ _ _ _ (Ref: 8.8) ---------------- --- --------------------------- -------- ---------- | Addressing Mode | Assembly | No. Bytes | No. Cycles | ----------------------------- ------------ ---------- --------- -------- ---------- | Implied | TXS | 9A | 1 | 2 | ---------------- --------------------- --- ---- --------- ---------- TYA TYA TRANSFER INDEX Y To Accumulator TYA

Operation: y -> a nzcidv / / _ _ _ _ _ (ref: 7.14) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------- --------- -------- ---------- | Addressing Mode | Assembly Language Form | OP Code | NO. BYTES | NO. CYCLES | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - --------- --------- ---------- | Implied | TYA | 98 | 1 | 2 | ----- ----------- ------------------------------- ---- ----- ----------

----------------------------------- ----------------------- | instruction addressing modes and related execution times | (in clock cycles) ------------ -------------------------------------------------- ------------

A A A A B B B B B B B B B C D N S C C E I M N P R V V1.. I....................... S........................................................... 4 * 7....................................................... RELATIVE |..................................... Indirect, Y | 5 * 5 * ".................

-------------------------------------------------- --------- C C C C C D D D e i i j l L M P P E E E o N N m D i v P x y c x y r c x y S..................................... Swash........................................................................................................................................................... 6......................................................................................................... Rs................. (Indirect, x) | ............................. 5 ----------------------------------------------------------------------------------------- -------------- * Add One Cycle if Indexing Across Page Border ** Add One Cycle If Branch Is Taken, Add One Additional IF Branching Operation Crosses Page Boundary -------- -------------------------------------------------- -------------- Instruction Addressing Modes and related Execution Times | --------------------- -------------------------------------------------- -

J l L L N o p p p r R R S D D s O R h L O O T R A x Y R P A A P A P L R I Accumulator |..... IMediate |. 2 2......................... Zer................................................................................................. 4 *. 4 * 7. 4 *.. 7. Absolute, y |. 4 * 4 *............................ "Indirect, x) |. 6........................ Sign................

-------------------------------------------------- ------- r s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s x x y x y ............................................... Zeero page, x |........................... .................................................................................................................................................................................................... S...................... ..................................... -------------------------------------------------------------------------------------------------------- ------------- * Add One Cycle if Indexing Across Page Border ** Add ONE CYCLE IF BRANCH IS TAKEN, ADD One Additional IF Branching Operation Crosses Page Boundary

00 - BRK 20 - JSR 01 - ORA - (Indirect, x) 21 - And - (Indirect, X) 02 - Future Expansion 22 - Future Expansion 03 - Future Expansion 23 - Future Expansion 04 - Future Expansion 24 - Bit - Zero Page 05 - ORA - ZERO Page 25 - And - Zero Page 06 - ASL - ZERO Page 26 - ROL - ZERO Page 07 - FUTURE Expansion 27 - Future Expansion 08 - PHP 28 - PLP 09 - ORA - Immediate 29 - And - Immediate 0a - IMMEDIATE 0A ASL - Accumulator 2A - ROL - Accumulator 0B - Future Expansion 2B - Future Expansion 0C - Future Expansion 2C - BIT - Absolute 0D - ORA - Absolute 2D - AND - Absolute 0E - ASL - Absolute 2E - ROL - Absolute 0F - Future Expansion 2F - FUTURE Expansion 10 - BPL 30 - BMI 11 - ORA - (Indirect), Y 31 - And - (Indirect), Y 12 - Future Expansion 32 - Future Expansion 13 - Future Expansion 33 - Future Expansion 34 - Future Expansion 15 - Ora - Zero Page, x 35 - And - Zero Page, x 16 - Asl - Zero Page, x 17 - Rol - Zero Page, x 17 - Future Expansion 37 - Future Expansion 18 - CLC 38 - Sec 19 - Ora - Absolute, Y 39 - And - Absolute, Y 1A - Future Expansion 3A - FUTURE Expansion 1b - Future Expansion 3b - Future Expansion 1C - Future Expansion 3c - Future Expansion 1D - ORA - ABSOLUTE,

X 3d - And - Absolute, x 1e - ASL - ABSOLUTE, X 3E - ROL - ABSOLUTE, X 1F - Future Expansion 3F - Future Expansion

40 - RTI 60 - RTS 41 - EOR - (Indirect, x) 61 - ADC - (Indirect, x) 42 - Future Expansion 62 - Future Expansion 63 - Future Expansion 44 - Future Expansion 64 - Future Expansion 45 - EOR - ZERO Page 46 - ADC - ZERO Page 66 - ROR - ZERO Page 66 - ROR - ZERO Page 47 - Future Expansion 67 - Future Expansion 48 - PHA 68 - PLA 49 - EOR - Immediate 69 - ADC - Immediate 4a - lsr - iv- Accumulator 6A - ROR - Accumulator 4B - Future Expansion 6B - Future Expansion 4C - JMP - Absolute 6C - JMP - Indirect 4D - EOR - Absolute 6D - ADC - Absolute 4E - LSR - Absolute 6E - ROR - Absolute 4F - Future Expansion 6F - FUTURE Expansion 50 - BVC 70 - BVS 51 - EOR - (Indirect), Y 71 - FUTURE Expans 72 - Future Expansion 53 - Future Expansion 73 - Future Expansion 54 - Future Expansion 74 - Future Expansion 55 - EOR - ZERO Page, x 75 - ADC - Zero Page, x 56 - LSR - Zero Page, x 76 - ROR - ZERO PAGE, X 57 - FUTURE Expansion 77 - Future Expansion 58 - CLI 78 - SEI 59 - EOR - ABSOLUTE, Y 79 - ADC - ABSOLUTE, Y 5A - FUTURE Expansion 7A - FUTURE Expansion 5b - Future Expansion 7b - Future Expansion 5c - Future Expansion 7c - Future Expansion 50 - EOR - ABSOLUTE,

X 70 - ADC - Absolute, X 5E - LSR - Absolute, X 7E - ROR - ABSOLUTE, X 5F - Future Expansion 7F - Future Expansion

80 - FUTURE Expansion A0 - LDY - Immediate 81 - Sta - (Indirect, x) A1 - LDA - (Indirect, x) 82 - Future Expansion A2 - LDX - Immediate 83 - Future Expansion A3 - FUTURE Expansion 84 - Sty - Zero Page A4 - LDY - Zero Page 85 - Sta - Zero Page 86 - StX - Zero Page A6 - LDX - ZERO Page 87 - Future Expansion A7 - FUTURE Expansion 88 - Dey A8 - TAY 89 - FUTURE Expansion A9 - LDA - Immediate 8A - TXA AA - TAX 8B - Future Expansion AB - Future Expansion 8C - STY - Absolute AC - LDY - Absolute 80 - STA - Absolute AD - LDA - Absolute 8E - STX - Absolute AE - LDX - Absolute 8F - Future Expansion AF - FUTURE Expansion 90 - BCC B0 - BCS 91 - STA - Indirect), Y B1 - LDA - (Indirect), Y 92 - Future Expansion B2 - Future Expansion 93 - Future Expansion B3 - Future Expansion 94 - Sty - Zero Page, x 95 - Sta - ZERO Page, x BS - LDA - Zero Page, Y B6 - LDX - ZERO PAGE, Y 97 - FUTURE Expansion B7 - FUTURE Expansion 98 - TYA B8 - CLV 99 - Sta - Absolute, Y B9 - LDA - ABSOLUTE, Y 9A - TXS BA - TSX 9B - FUTURE Expanson BB - Future Expansion 9c - Future Expansion BC - LDY - Absolute, X 90 - Sta - Absolute, X BD - LDA - Absolute,

X 9E - FUTURE EXPANSION BE - LDX - ABSOLUTE, Y 9F - FUTURE Expanson BF - FUTURE Expansionc0 - CPY - IMMEDIATE E0 - CPX - Immediate C1 - CMP - (Indirect, x) E1 - SBC - (Indirect, x) C2 - FUTURE Expansion E2 - FUTURE EXPANSION C3 - FUTURE Expansion E3 - FUTURE Expansion C4 - CPY - ZERO Page E4 - CPX - Zero Page E5 - SBC - Zero Page C6 - DEC - ZERO Page E6 - Inc - Zero Page C7 - FUTURE Expansion E7 - FUTURE E8 - INY E8 - Inx C9 - CMP - Immediate E9 - SBC - IMMEDIATE CA - DEX EB - NOP CB - FUTURE Expansion EB - FUTURE Expansion CC - CPY - ABSOLUTE EC - CPX - Absolute CD - CMP - Absolute ED - SBC - Absolute CE - DEC - ABSOLUTE EE - INC - ABSOLUTE CF - FUTURE EXPANSION EF - FUTURE Expansion D0 - BNE F0 - BEQ D1 - CMP (Indirect @

, Y F1 - SBC - (Indirect), Y D2 - FUTURE Expansion F2 - FUTURE Expansion D3 - FUTURE Expansion F3 - FUTURE Expansion D4 - FUTURE Expansion F4 - FUTURE Expansion D5 - Cmp - Zero Page, X F5 - SBC - Zero Page, X D6 - DEC - ZERO PAGE, X D7 - FUTURE Expansion F7 - FUTURE Expansion D8 - CLD F8 - SED D9 - CMP - ABSOLUTE, Y F9 - SBC - Absolute, Y DA - FUTURE Expansion FA - Future Expansion DB - Future Expansion FB - Future Expansion DC - Future Expansion FC - Future Expansion DD - CMP - Absolute, X FD - SBC - Absolute, X DE - DEC - Absolute, X FE - INC - Absolute, X DF - Future Expansion FF - FUTURE ExpansionStruction Operation

The Following Code Has Been Taken From Vice For the Purpos'. No Particular Addressing Mode Is Used SinceweWe Only Wish To See The Operation of The Instruction Itself.

src: the byte of data that is being addressed SET_SIGN:. sets / resets the sign flag depending on bit 7. SET_ZERO: sets / resets the zero flag depending on whether the result is zero or not SET_CARRY (condition):. if the condition has a non-zero value then the carry flag is set, else it is reset SET_OVERFLOW (condition):. if the condition is true then the overflow flag is set, else it is reset SET_INTERRUPT:.} SET_BREAK:} As for SET_CARRY and SET_OVERFLOW SET_DECIMAL:.} REL_ADDR (PC, src): returns the relative address obtained by adding the displacement src to the PC SET_SR:. set the Program Status Register to the value given GET_SR:.. get the value of the Program Status Register PULL : PULL A BYTE OFF The Stack. Push: Push A Byte ONTO The Stack. Load: Get A Byte From The Memory Address. Store: Store A Byte In A Memory Address. If_carry, if_overflo W, IF_SIGN, IF_ZERO etc: Returns true if the relevant flag is set, otherwise returns false clk:. The number of cycles an instruction takes This is shown below in situations where the number of cycles changes depending on the result of the instruction (. Eg. branching instructions .ac = Accumulator xr = x register yr = y register pc = program counter sp = stack pointer

/ * ADC * / unsigned int TEMP = SRC AC (if_carry ()? 1: 0); set_zero (TEMP & 0xFF); / * this is not valid in decimal mode * / if (if_decimal ()) {ix (= ((AC & 0xF) (SRC & 0xF) (if_carry ()? 1: 0)> 9) TEMP = 6; set_sign (TEMP); set_overflow (! (AC ^ src) & 0x80) && (AC ^ Temp) & 0x80)); IF (Temp> 0x99) TEMP = 96; set_carry (Temp> 0x99);} else {set_sign (TEMP); set_overflow (! ((AC ^ src) & 0x80) && (Ac ^ TEMP) & 0x80)); set_carry (TEMP> 0xFF);} ac = ((byte) Temp); / * and * / src & = ac; set_sign (src); set_zero (src); AC = src ;

/ * ASL * / SET_CARRY (SRC & 0x80); SRC << = 1; SRC & = 0xFF; set_sign (src); SET_ZERO (SRC); Store SRC IN MEMORY OR ACCULATOR Depending On Addressing Mode.

/ * Bcc * / if (! If_carry ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC);

/ * BCS * / IF (if_carry ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC);

/ * Beq * / if (if_zero ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = REL_ADDR (PC, SRC);

/ * Bit * / set_sign (src); set_overflow (0x40 & src); / * Copy bit 6 to overflow flag. * / Set_zero (src & ac);

/ * Bmi * / if (if_sign ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC);

/ * Bne * / if (! If_zero ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = REL_ADDR (PC, SRC);}

/ * Bpl * / if (! If_sign ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC); / * BRK * / PC ; Push ((PC >> 8) & 0xff); / * push return address ONTO the stack. * / Push (PC & 0xFF); set_break ((1)); / * set bflag before pushing * / Push (sr); set_interrupt ((1)); PC = (LOAD (0xfff) << 8));

/ * BVC * / if (! If_overflow ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC);

/ * BVS * / IF (if_overflow ()) {CLK = ((PC & 0xFF00)! = (REL_ADDR (PC, SRC) & 0xFF00)? 2: 1); PC = Rel_Addr (PC, SRC);

/ * CLC * / set_carry ((0));

/ * CLD * / set_decimal ((0));

/ * CLI * / set_interrupt ((0));

/ * CLV * / set_Overflow ((0));

/ * Cmp * / src = ac - src; set_carry (SRC <0x100); set_sign (src); set_zero (src & = 0xFF);

/ * Cpx * / src = XR - src; set_carry (SRC <0x100); set_sign (src); set_zero (src & = 0xFF);

/ * CPY * / src = yr - src; set_carry (SRC <0x100); set_sign (src); set_zero (src & = 0xFF);

/ * DEC * / SRC = (SRC - 1) & 0xFF; set_sign (src); set_zero (src); Store (Address, (SRC));

/ * DEX * / unsigned SRC = XR; SRC = (SRC - 1) & 0xff; set_sign (src); set_zero (src); XR = (SRC);

/ * Dey * / unsigned src = yr; src = (SRC - 1) & 0xff; set_sign (src); set_zero (src); yr = (src);

/ * EOR * / src ^ = ac; set_sign (src); set_zero (src); AC = src;

/ * Inc * / src = (src 1) & 0xff; set_sign (src); set_zero (src); store (address, (src)); / * Inx * / unsigned src = xr; src = (SRC 1 ) & 0xff; set_sign (src); set_zero (src); XR = (src);

/ * Iny * / unsigned SRC = YR; SRC = (SRC 1) & 0xFF; set_sign (src); set_zero (src); yr = (src);

/ * JMP * / PC = (SRC);

/ * JSR * / PC -; Push (PC >> 8) & 0xff); / * Push Return Address ONTO The Stack. * / Push (PC & 0xFF); PC = (SRC);

/ * LDA * / set_sign (src); set_zero (src); AC = (SRC);

/ * LDX * / set_sign (src); set_zero (src); XR = (src);

/ * LDY * / set_sign (src); set_zero (src); yr = (src);

/ * LSR * / set_carry (src & 0x01); SRC >> = 1; set_sign (src); set_zero (src); Store SRC IN Memory or Accumulator Depending ON Addressing Mode.

/ * NOP * / NOTHING.

/ * ORA * / SRC | = AC; set_sign (src); set_zero (src); ac = src;

/ * PHA * / SRC = AC; Push (src);

/ * PHP * / src = GET_SR; Push (src);

/ * PLA * / SRC = PULL (); set_sign (src); / * Change Sign and Zero Flag Accordingly. * / Set_zero (src);

/ * PLP * / src = PULL (); set_sr ((src));

/ * Rol * / src << = 1; if (if_carry ()) src | = 0x1; set_carry (src> 0xFF); SRC & = 0xff; set_sign (src); set_zero (src); Store Src in Memory or Accumulator Depending on addressing mode.

/ * ROR * / IF (if_carry ()) src | = 0x100; SET_CARRY (SRC & 0x01); SRC >> = 1; set_sign (src); SET_ZERO (SRC); Store Src in Memory or Accumulator Depending ON Addressing Mode.

/ * RTI * / SRC = PULL (); set_sr (src); src = PULL (); SRC | = (PULL () << 8); / * load return address from stack. * / Pc = (src); / * RTS * / SRC = PULL (); SRC = (()) << 8) 1; / * load return address from stack and add 1. * / pc = (src);

/ * SBC * / unsigned int TEMP = AC - SRC - (if_carry ()? 0: 1); set_sign (TEMP); set_zero (TEMP & 0xFF); / * Sign and Zero Are INVALID IN DECIMAL MODE * / SET_OVERFLOW (( (AC ^ Temp) & 0x80) && ((ac ^ src) & 0x80); if (if_decimal ()) {IF (((AC & 0xF) - (if_carry ()? 0: 1)) <(SRC & 0xF)) / * EP * / TEMP - = 6; if (TEMP> 0x99) TEMP - = 0x60;} set_carry (Temp <0x100); AC = (TEMP & 0xFF);

/ * Sec * / set_carry ((1));

/ * SED * / set_decimal ((1));

/ * SEI * / set_interrupt ((1));

/ * STA * / Store (Address, (src));

/ * Stx * / Store (Address, (SRC));

/ * STY * / STORE (Address, (src));

/ * Tax * / unsigned src = ac; set_sign (src); set_zero (src); XR = (SRC);

/ * Tay * / unsigned src = ac; set_sign (src); set_zero (src); yr = (src);

/ * TSX * / unsigned src = sp; set_sign (src); set_zero (src); XR = (SRC);

/ * Txa * / unsigned SRC = XR; set_sign (src); set_zero (src); AC = (src);

/ * Txs * / unsigned SRC = XR; SP = (SRC);

/ * TYA * / Unsigned SRC = YR; set_sign (src); set_zero (src); AC = (SRC);

Author: RockCarry studio Chen Kai 2005.2.10 Copyright if reproduced please indicate the source

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