From: http://www.pconline.com.cn/diy/evalue/evalue/storage/0210/284937.htmlauthor: Huang Wen Date: 2002-10-10
To explore the SERIAL ATA technology, we must first simply analyze the differences between works between ATA and SERIAL ATA:
1. Influence of data transfer cycle on transmission speed
First, let's first explore the impact of data transfer cycles on transmission speed. The current parallel ATA standard uses 16bit two-way bus, that is, 1 data transfer cycle can transmit 4 bytes of data (1 byte = 8bit, 16bit two-way bus one cycle can transmit 16bit / 8 × 2 bytes) ), While everyone can use Ultra ATA 100 per second to transmit 100MB (100000000 bytes) data, through a simple formula:
Frequency × data transfer rate of one cycle = data transmission rate per second
By calculating the clock frequency of the Ultra ATA100, it is a clock frequency that is 25MHz phase-transmitted clock frequencies that the Ultra ATA interface technology specification is also included with us 25000000Hz (25 MHz). The same, one cycle is 40ns (unit time / frequency: 1s / 25MHz).
Various Ultra ATA interface specifications list:
To explore the SERIAL ATA technology, we must first simply analyze the differences between works between ATA and SERIAL ATA:
1. Influence of data transfer cycle on transmission speed
First, let's first explore the impact of data transfer cycles on transmission speed. The current parallel ATA standard uses 16bit two-way bus, that is, 1 data transfer cycle can transmit 4 bytes of data (1 byte = 8bit, 16bit two-way bus one cycle can transmit 16bit / 8 × 2 bytes) ), While everyone can use Ultra ATA 100 per second to transmit 100MB (100000000 bytes) data, through a simple formula:
Frequency × data transfer rate of one cycle = data transmission rate per second
By calculating the clock frequency of the Ultra ATA100, it is a clock frequency that is 25MHz phase-transmitted clock frequencies that the Ultra ATA interface technology specification is also included with us 25000000Hz (25 MHz). The same, one cycle is 40ns (unit time / frequency: 1s / 25MHz).
Various Ultra ATA interface specifications list:
Ultra DMA Data Transfer Period:
However, in the data transfer, there is a time interval between two consecutive data transfer cycles, the interval is half a clock cycle, that is, 20ns, but in the other half clock cycle including adjustment period, keeping and maximum Data transfer time. The maintenance period means that the data needs to be maintained after the transfer is completed, and there is another adjustment time in the two data transfer. During this time, the preparation of transmitted data is required, and the ATAPI-6 protocol specified for adjustment The period and the maintenance period is 4.8ns, and the remaining 10.4ns time is the largest data transfer time.
What is the relationship between transport cycle and transmission speed? To increase the transmission speed, reduce the waiting time (including the time interval between two consecutive clocks, the adjustment period, and hold period), the easiest way is to shorten the entire transfer cycle, so the Ultra ATA 133 standard increases the clock frequency to 33.3 MHZ, so the half cycle is shortened to 15ns, but in the ATAPI-6 protocol, the adjustment period and the maintenance period are 4.8ns, which will not change, so the ATA 133 has only 5.4ns of data transmission time, which will be currently possible. The fastest speed. The 8-bit bus of the SERIAL ATA point-to-point direct transmission, according to the Serial ATA data transfer specification: Serial ATA's clock frequency is 150MHz, 150MHz × 8bit (1 byte) = 150MB, this is just the current transmission rate of the first generation Serial ATA. By 150MHz clock frequency can easily calculate only 0.333ns (1 cycle = 1 / 150m), the waiting and data adjustment time during the transmission process will also be reduced accordingly, so it greatly improves the transmission speed, this Also serial ATA can easily go to 1.5Gbit / s, but 0.333ns is just the beginning of Serial ATA, and there is still great development in the future.
2. Different from the implantable clock system in parallel ATA
What can SERIAL ATA can reach so high frequency? The reason is that Serial ATA and parallel ATA are different depending on the external clock signal, and the Serial ATA has an implantable clock that can be used when processing signals and data. This implantable clock is actually the same as the data itself as the clock signal. This is the only potential question is that when there is no data transmission, the data and data on the memory are not necessarily synchronized. However, this problem can be easily resolved, and "Dummy Singnal" is transmitted when idle, as "101010" meaningless signals to maintain both synchronization, because there is no parallel device, the signal does not appear inconsistent.
3. Transmission mode limits the high working frequency
Then will you ask the parallel ATA not to increase the transmission frequency? The answer is not too high, Ultra ATA uses the usual non-interlocking clock signal, and it is easy to cause any difference in the electrical properties of the line when the frequency is too high, which can bring the mismatch of the clock signal, causing the data arrival time and the transmission signal. And even pass the data to the other data receiver. Then, the standard voltage of the parallel ATA is 5V, even the ATA 100 is 3.3V, whenever the data is transmitted in the data line, the data line of the parallel ATA is like a transformer, the length and voltage change of the cable is generated. The changed electromagnetic field affects the data transfer in other data lines. If the interference in parallel ATA rates, this interference will rise straight. Therefore, when ATA 33 turns into ATA 100, there is 40 shields on the flat data line, so that between signal lines, power cords, control lines are separated from one wire, which can effectively reduce interference, but this The method of solving is not possible to continue to develop.
For the Serial ATA, the low voltage differential signal (LVDS) technology and the plus data cable design are easily solved the problem of electromagnetic field interference. LVDS refers to an advanced signal transmission mode that transmits two voltage signals through a pair of lines, and between the two voltages is actual data, and the lower voltage can be used to get a faster transmission speed. Because the number of electrons to be propagated, the speed increases by the same frequency. Data cable two-way transmission data only requires 4 data cables, plus ground lines to provide corresponding shielding, ensuring that electromagnetic field interference is generated when data transmission, and the number of lines is reduced from the 80 line of Ultra ATA to 20 lines, in fact, serial The ATA is not arranged in parallel, and the shield line is implemented by coaxial package data line, which allows the data cable to continue to increase the diameter, reduce impedance, improve anti-interference capability, and further increase the transmission speed. Serial ATA features:
1. Lighter, more flexible wiring
I believe that the friends of the standing machine must have a deep understanding, the most troublesome in the chassis are all kinds of wiring, which is neither aesthetics, especially the thick data cable, and its longest distance is only 40 cm, installation The upper is not flexible, to install the hard disk in the uppermost machine of the large-scale upright chassis, not only this, not only this, its interface has positive and negative points, often in order to install the hard disk in a specific location, we still have to turn off to reverse One hundred and eighty degrees, if you have to install 2 devices on a data line, then the result is really not imagined.
And when you see the Serial ATA's data line, you can't help but hay. Its wiring can be as long as one meter, the shape is exquisite, even the joint between the two ends of the width of the wiring is only about 1 cm. Even if you distorted, the knot does not affect its normal work. The most worthpass is that its interface is not a pin design, but the contact piece of the tile, I don't know if you have the Ultra ATA's data cable to pull out the hard disk, then pull out together, that I can't help why, and the Serial ATA will make this worry.
2. Want to support the hot swap
For users who often play hardware, Serial ATA's interface supports hot-swappable features that make them the most delightful. The interface of Serial ATA is unidirerative. Due to the design of the anti-insert error on the interface, the interface is long, so you will not insert the wrong; due to the use of needle district design, there are two lengths in the interface. The needle can be achieved in order, and the longest needle is always first first, and then the short needle. Serial ATA uses the inside of the interface as a ground wire. This is a simple and practical design. With the "grounding" processing, "discharge phenomenon" This maximum problem that implements the thermal plugging of the equipment can be properly solved. That is, when an apparatus is added to the system, the long needle is first contacted, which is a balance in the electrical sense to protect other data lines, and the device is connected in accordance with the set order, and the host is established. Thus heat-swapping. With hot-swappable technology, you can increase the Serial ATA device at any time, and newer operating systems can automatically identify new devices (system after Windows 98SE), implement plug and play.
