Simple example using Makefile
Use an example to explain how to write Makefile.
Source code:
// file: a.h
#ifndef a_h
#define a_h
Class a {
PUBLIC:
A ();
~ A ();
Void f ();
}
#ENDIF / / A_H
// file: a.cpp
#include "a.h"
A :: a () {
}
A :: ~ () {
}
Void a :: f () {
}
// file: b.h
#ifndef b_h
#define b_h
Class b {
PUBLIC:
B ();
~ ();
Void g ();
}
#ENDIF / / B_H
// file: b.cpp
#include "b.h"
B :: b () {
}
B :: ~ b () {
}
Void b :: g () {
}
// file: main.cpp
#include "a.h"
#include "b.h"
int main ()
{
A a a;
B B;
B.G ();
Return 0;
}
The organizational form of the above source program should be the most common. So now you have to write
A Makefile file allows the compiler to compile.
First, the Makefile file is composed of one one-to-one target dependent command.
Usually such a command is divided into two lines, the second line is usually
It is a compilation connection command. And the head is to start with the
The Make program will perform these commands.
Second, the goal is the form of the command
Target: Dependencies
Now I have to figure out, what kind of compilation command is used. Because it is on UNIX / Linux,
So nature should be CC / GCC / G .
Also clear: The final executable target program is made by all .cpp files
After compiling .o files together.
Ok, now start writing the Makefile file.
We assume that the last generated executable target name is Exam.
#comment, Start with # (Sharp)
Exam: main.o a.o b.o
G main.o a.o B.O -O Exam
Main.o: main.cpp a.h b.h
G -c main.cpp -o main.o
a.o: a.cpp a.h
G -c a.cpp -o a.o
B.O: B.CPP B.H
G -c b.cpp -o b.o
#makefile end
Please note that each command starts with the
After writing, put it in the directory where the source file is located.
Then run
$ Make
I will see the compile command you use.
Of course, macro variables can be used in the makefile file. This is convenient when you write at least a point.
First introduce three special predefined macro variables.
$ @ 指 当 Current Target Name (Target)
$ ^ Refers to the current entire dependent file list (dependencies)
$ As can be seen from the above description, you can use a macro variable instead of a list of files. So how do you reference these macro variables later? It is the name of the variable with the symbol $. Note: If the macro variable name is more than one, you should use parentheses to parentheses $ (Name). Defining the format of macro variables is Macro_name = String1 String2 ... Here String can be a file name, or a compiler parameter, etc. Ok, now make some changes to Makefile just now. #makefile using macro variantsobjs = main.o a.o b.o CC = G Exam: $ (OBJS) $ (Cc) $ ^ -o $ @ Main.o: main.cpp a.h b.h $ (Cc) -c $-@ @ @ a.o: a.cpp a.h $ (Cc) -c $-@ @ @ B.O: B.CPP B.H $ (Cc) -c $-@ @ @ #makefile end Basically this is a very common Makefile. After the compilation is complete, there will be a lot of .o files. To clear them, you can do it in makefile. How to do it? Add the following command to the end of the file: Clean: RM -F * .O Then, run the command $ make Clean Come. Explain to the last command. Clean is a target name. It can also be replaced with other, such as Cleanup. Then the Make Clean command that is running is to let the Make program complete the specified target.
