D x86 inline assembly
D. As a system programming language, the function of the inline assembly is provided. For the same processor family, the implementation of the inline assembly of D is standardized, for example, the syntax of the inline assembly of the Win32 D compiler on Intel Pentium is the same as the syntax of the Linux D compiler on Intel Pentium. of.
However, different D is implemented in accordance with the memory model, the function call / return, and the parameter delivery will be freely realized.
This article describes the X86 implementation of the inline assembly.
ASM directive:
Marking: ASM Directive
Align integer expression
Even
naked
DB multiple operands
DS multiple operands
Di multiple operands
DL multiple operands
DF multiple operands
DD multiple operands
DE multiple operands
Operate code
Multiple operands
Multiple operands
Operand
Operation, multiple operands
Asminstruction:
Identifier: asminstruction
Align Integerexpression
Even
naked
DB Operands
DS OPERANDS
Di Operands
DL Operands
DF OPERANDS
DD OPERANDS
de Operands
Opcode
Opcode Operands
Operands
Operand
Operands, Operands
The label assembly instructions can be labeled as other statements. They can be used as a goal of a goto statement. E.g:
Void * pc;
ASM
{
Call L1;
L1:;
POP EBX;
MOV PC [EBP], EBX; // PC Now pointing to L1
}
Align integer expression assembler uses NOP instructions to fill, so that the next instruction is aligned
Integer expressions.
The value of an integer expression must be a power of 2.
Align the loop code allows the execution speed to be improved.
EVEN assembler is filled with NOP instructions to align the next instruction to the even boundary.
Naked prohibits the compiler generates the framework of the function and the decomposition instruction. This means that the responsibility has fallen on the header of the programmer who uses the inline, so this usage is mainly used in all the functions written by the inner contract.
DB, DS, DI, DL, DF, DD, DE These pseudo operations are inserted directly into the code into the original data.
DB is used for bytes,
DS is used for 16-bit words,
DI is used for 32-bit words,
DL is used for 64 characters,
DF is used in 32-bit floating point,
DD is used for 64-bit double-precision types,
DE is used for 80-bit expansion real numbers. They are all applicable to multiple operands. If there is an operand as a string, the assembler thinks there is an implicit
Length operand,
Length indicates how many characters in the string. Each operand will additionally use a character. E.g:
ASM
{
DB 5, 6, 0x83; // Insert BYTE 0x05, 0x06 and 0x83
DS 0x1234; // Insert BYTE 0x34, 0x12
Di 0x1234; // Insert BYTE 0x34, 0x12, 0x00, 0x00
DL 0x1234; // Insert BYTE 0x34, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
DF 1.234; // Insert FLOAT 1.234
DD 1.234; // Insert Double 1.234
DE 1.234; // Insert Extended 1.234
DB "abc"; // Insert BYTE 0x61, 0x62, and 0x63
DS "abc"; // Insert BYTE 0x61, 0x00, 0x62, 0x00, 0x63, 0x00}
The supported opcode is listed at the end of this article.
Support the following registers. The register name is capitalized.
Al,
AH,
AX,
EAX
BL,
BH,
BX,
EBX
CL,
CH,
CX,
ECX
DL,
DH,
DX,
EDX
BP,
EBP
SP,
ESP
Di,
EDI
Si,
ESI
ES,
CS,
SS,
DS,
GS,
FS
CR0,
CR2,
CR3,
CR4
DR0,
DR1,
DR2,
DR3,
DR6,
DR7
TR3,
TR4,
TR5,
TR6,
TR7
ST
ST (0),
ST (1),
ST (2),
ST (3),
ST (4),
ST (5),
ST (6),
ST (7)
MM0,
MM1,
MM2,
MM3,
MM4,
MM5,
MM6,
MM7
Special case
LOCK,
REP,
REPE,
Repne,
RepNZ,
REPZ
These prefix instructions cannot be located in the same statement with their modified instructions, which must be written separately into one instruction. E.g:
ASM
{
REP;
Movsb;
}
PAUSE
Inline assembly does not support this operation code, use
{
REP;
NOP;
}
Instead, the effect is the same.
Floating point operation
Use the number of operations of the instruction:
FDIV ST (1); // Error
Fmul st; // error
FDIV ST, ST (1); / / correct
Fmul st, st (0); // correct
operating
Action:
ASM expression
ASM expression:
ASM logic or expression
ASM logic or expression? ASM expression: ASM expression
ASM logic or expression:
ASM logic and expression
ASM logic and expressions || ASM logic and expressions
ASM logic and expression:
ASM or expression
ASM or Expression && ASM or expression
ASM or expression:
ASM different or expressive
ASM is or expression | ASM is different or express
ASM is too or expressive:
ASM and expression
ASM and expression ^ ASM and expressions
ASM and expression:
ASM equal expression
ASM equal expression & asm equivalent expression
ASM equal expression:
ASM relationship expression
ASM relationship expression == ASM relationship expression
ASM relationship expression! = ASM relationship expression
ASM relationship expression:
ASM shift expression
ASM shift expression ASM shift expression <= ASM shift expression ASM shift expression> ASM shift expression ASM shift expression> = ASM shift expression ASM shift expression: ASM and expressions ASM and expressions << ASM and expressions ASM and Expression >> ASM and Expression ASM and expression >>> ASM and expressions ASM and expressions: ASM volume list ASM volume list ASM volume list ASM volume list - ASM volume list ASM volume list: ASM brackets express ASM Braces Expressions * ASM Braces Expressions ASM Braces Expression / ASM Brand Expression ASM bracket expression% ASM bracket expression ASM Braces Expression: ASM 1 yuan expressions ASM bracket expression [ASM expression] ASM 1 yuan express: ASM type prefix ASM expression Offset ASM Expression SEG ASM expression ASM 1 yuan expressions - ASM 1 yuan expressions ! ASM 1 yuan expressions ~ ASM 1 yuan expressions ASM basic expression ASM basic expression Integer constant Floating point constant __Local_size $ register Point sign Point sign Identifier Mark symbol. Point sign Operand: Asmexp Asmexp: Asmlogorexp AskLOGOREXP? Asmexp: asmexp AsmlogorExp: Asmlogandexp AskLOGANDEXP || Asmlogandexp Asmlogandexp: Asmorexp Asmorexp && asmorexp Asmorexp: Asmxorexp Asmxorexp | asmxorexp Asmxorexp: Asmandexp AskAMANDEXP ^ Asmandexp Asmandexp: AsMequalexP AskQUALEXP & AsMequaleXP AsMequalexp: Asmrelexp Asmrelexp == asmrelexp Asmrelexp! = Asmrelexp Asmrelexp: Asmshiftexp Asmshiftexp Asmshiftexp <= asmshiftexp AskSHIFTEXP> Asmshiftexp AskSHIFTEXP> = asmshiftexp AskSHIFTEXP: Asmaddexp Asmaddexp << asmaddexp Asmaddexp >> asmaddexp AsmadDexp >>> asmaddexp Asmaddexp: Asmmulexp AskMMULEXP ASMMULEXP AsmmulexP - AsmmulexP Asmmulexp: Asmbrexp AskBREXP * ASMBREXP AskBREXP / Asmbrexp AskBREXP% asmbrexp Ask: ASMBREXP: Asmunaexp AskBREXP [Asmexp] Asmunaexp: Asmtypeprefix asmexp Offset asmexp SEG Asmexp Asmunaexp - asmunaexp ! Asmunaexp ~ Asmunaexp AskPRIMARYEXP AskPRIMARYEXP INTEGERCONSTANT FloatConstant __Local_size $ Register Dotidentifier Dotidentifier Identifier Identifier. Dotidentifier The syntax of the operand is basically comparable to the agreement of the Intel CPU documentation. Specifically, the number of operands on the right is the source operand, and the operand on the left is the number of operands. The existence of Intel is mainly compatible with the target of the D language symbol identifier and simple parsing. Operating type ASM type prefix: Near PTR FAR PTR BYTE PTR Short Ptr Int Ptr Word Ptr DWORD PTR Float Ptr Double PTR Extended PTR Asmtypeprefix: Near PTR FAR PTR BYTE PTR Short Ptr Int Ptr Word Ptr DWORD PTR Float Ptr Double PTR Extended PTR For the operating size of the operating size, like: Add [EAX], 3; can use ASM type prefix eliminates ambiguity: Add Byte Ptr [EAX], 3; Add Int Ptr [EAX], 7; Structure / Combined / class member offset hypothesis points to the aggregated pointers located in a register, and if you want to access the aggregated member, you should use the member's qualified name: Struct foo {Int A, B, C;} int BAR (foo * f) { ASM {MOV EBX, F; Mov Eax, foo.b [ebx]; } } Special symbol $ Represents the start address of the next instruction. and so, JMP $; will jump to the instruction after JMP. __Local_size Its value is replaced by the number of local bytes in the local stack frame. Use This will be convenient when Naked and manually develop a stack structure. Supported opcode aaaaadaamaasadcaddaddpdaddpsaddsdaddssandandnpdandnpsandpdandpsarplboundbsfbsrbswapbtbtcbtrbtscallcbwcdqclccldclflushclicltscmccmovacmovaecmovbcmovbecmovccmovecmovgcmovgecmovlcmovlecmovnacmovnaecmovnbcmovnbecmovnccmovnecmovngcmovngecmovnlcmovnlecmovnocmovnpcmovnscmovnzcmovocmovpcmovpecmovpocmovscmovzcmpcmppdcmppscmpscmpsbcmpsdcmpsscmpswcmpxch8bcmpxchgcomisdcomisscpuidcvtdq2pdcvtdq2pscvtpd2dqcvtpd2picvtpd2pscvtpi2pdcvtpi2pscvtps2dqcvtps2pdcvtps2picvtsd2sicvtsd2sscvtsi2sdcvtsi2sscvtss2sdcvtss2sicvttpd2dqcvttpd2picvttps2dqcvttps2picvttsd2sicvttss2sicwdcwdedadaadasdbdddedecdfdidivdivpddivpsdivsddivssdldqdsdtdwemmsenterf2xm1fabsfaddfaddpfbldfbstpfchsfclexfcmovbfcmovbefcmovefcmovnbfcmovnbefcmovnefcmovnufcmovufcomfcomifcomipfcompfcomppfcosfdecstpfdisifdivfdivpfdivrfdivrpfeniffreefiaddficomficompfidivfidivrfildfimulfincstpfinitfistfistpfisubfisubrfldfld1fldcwfldenvfldl2efldl2tfldlg2fldln2fldpifldzfmulfmulpfnclexfndisifnenifninitfnopfnsavefnstcwfnstenvfnstswfpatanfpremfprem1fptanfrndintfrstorfs avefscalefsetpmfsinfsincosfsqrtfstfstcwfstenvfstpfstswfsubfsubpfsubrfsubrpftstfucomfucomifucomipfucompfucomppfwaitfxamfxchfxrstorfxsavefxtractfyl2xfyl2xp1hltidivimulinincinsinsbinsdinswintintoinvdinvlpgiretiretdjajaejbjbejcjcxzjejecxzjgjgejljlejmpjnajnaejnbjnbejncjnejngjngejnljnlejnojnpjnsjnzjojpjpejpojsjzlahflarldmxcsrldslealeaveleslfencelfslgdtlgslidtlldtlmswlocklodslodsblodsdlodswlooploopeloopneloopnzloopzlsllssltrmaskmovdqumaskmovqmaxpdmaxpsmaxsdmaxssmfenceminpdminpsminsdminssmovmovapdmovapsmovdmovdq2qmovdqamovdqumovhlpsmovhpdmovhpsmovlhpsmovlpdmovlpsmovmskpdmovmskpsmovntdqmovntimovntpdmovntpsmovntqmovqmovq2dqmovsmovsbmovsdmovssmovswmovsxmovupdmovupsmovzxmulmulpdmulpsmulsdmulssnegnopnotororpdorpsoutoutsoutsboutsdoutswpackssdwpacksswbpac kuswbpaddbpadddpaddqpaddsbpaddswpaddusbpadduswpaddwpandpandnpavgbpavgwpcmpeqbpcmpeqdpcmpeqwpcmpgtbpcmpgtdpcmpgtwpextrwpinsrwpmaddwdpmaxswpmaxubpminswpminubpmovmskbpmulhuwpmulhwpmullwpmuludqpoppopapopadpopfpopfdporprefetchntaprefetcht0prefetcht1prefetcht2psadbwpshufdpshufhwpshuflwpshufwpslldpslldqpsllqpsllwpsradpsrawpsrldpsrldqpsrlqpsrlwpsubbpsubdpsubqpsubsbpsubswpsubusbpsubuswpsubwpunpckhbwpunpckhdqpunpckhqdqpunpckhwdpunpcklbwpunpckldqpunpcklqdqpunpcklwdpushpushapushadpushfpushfdpxorrclrcppsrcpssrcrrdmsrrdpmcrdtscrepreperepnerepnzrepzretretfrolrorrsmrsqrtpsrsqrtsssahfsalsarsbbscasscasbscasdscaswsetasetaesetbsetbesetcsetesetgsetgesetlsetlesetnasetnaesetnbsetnbesetncsetnesetngsetngesetnlsetnlesetnosetnpsetnssetnzsetosetpsetpesetposetssetzsfencesgdtshlshldshrshrdshufpdshufpssidtsldtsmswsqrtpdsqrtpssqrtsdsqrtssstcstdstistmxcsrstosstosbstosdstoswstrsubsubpdsubpssubsdsubsssysentersysexittestucomisducomissud2unpckhpdunpckhpsunpcklpdunpcklpsverrverwwaitwbinvdwrmsrxaddxchgxlatxlatbxorxorpdxorps Supported AMD opcode PAVGUSBPF2IDPFACCPFADDPFCMPEQPFCMPGEPFCMPGTPFMAXPFMINPFMULPFNACCPFPNACCPFRCPFRCPIT1PFRCPIT2PFRSQIT1PFRSQRTPFSUBPFSUBRPI2FDPMULHRWPSWAPD
