Saliside - a layer of fusion is produced when the metal and silicide contact, is known as the metal silicide, this and Saliside. Siliside - a process that deposes (or covered?) silicide in the source leak area, such a process is called Siliside. Poliside - is also a process, aliquot silicide at the gate Poly.
AMU Atom Quality ADI AFTER DEVELOP INSPECTION After viewing AEI Erclock After checking AEI eruption, Alignment is placed in a straight line, a linear relationship between the voltage and current, reducing the resistance of contact, Anti-reflect coating anti-reflection layer Asher: A dry etching ASI photoresist Removal After the backside wafer back, back, back surface, back etching, BEAM-CURRENT, electron beam current BPSG: silicon glass Break containing borophos, stopped the key Cassette in the middle of the Stepper machine CD: critical Dimension Key Size Chamber Room Chart Chart CHILD LOT Substation CHIP (DIE) Grains CMP Chemical Mechanical Grinding Coater Light Clip (Machine) Coating Coating, Light Grinding Contact Hole Contact Window Control Wafer Control Critical Layer Important layer CVD chemical vapor deposition CYCLE TIME production cycle Defect Defect DEP: Deposit Deposition Descum pretreatment developer developing solution; development (machine) development DG: Dual Gate Double Di Water deionized water DIFFusion Diffusion DOPING DOSE Dose Downgrade Digest DRC: Design Rule Check Design Rule Check DRY CLEAN WAFER DUE DATE DUMMY WAFER Vegetation E / R: ETCH RATE EE EE ELE EE ELECTOR END POINT EXT: Electrostatic Discharge / Electrostatic Damage Electrostatic Ion Damage ET: ETCH Etching Exhaust exhaust (excluding air in line) Exposure exposure Fab factory FIB: Focused Ion BEAM Focus ion beam Field Oxide Field Oxidation layer flatness FOCUS Foundry FSG: Containing fluorine-containing silicone glass Furnace Cotube GOI: Gate Oxide Integrity Door Oxidation Layer Integrity HMDS Hexamethyldisil Azane, the water-baked wafer will apply a layer of compound to increase the photoresist and wafer surface, called HMDS HCI: Hot Carrier Injection Hot carrier injection HDP: High Density Plasma High Density Plasma HIGH-VOLTAGE High-voltage Hot Bake Baking ID Iddrawal, IMPLANT Implant Layer Hierarchy LDD: Lightly DOPED DRAIN Light Doped Local DEFOCUS Local Decofocity Media for Mechanic or Wastes Locos: Local Oxidation of Silicon Local Oxidation LOOP Tour LOT Batch MASK (RETIN) mask MERGE Metal VIA metal contact window MFG manufacturing portions MID-CURRENT MODULE department NIT: Si3N4 silicon nitride Non-critical non-important NP: N-DOPED PLUS (N ) N-weight Doped NW: N-DOPED WELL N-well OD: Oxide Definition Defining Oxide OM: Optic Microscope OOS OOC OOC OOC OOS OOS OOS OOS Benefits OOM OOS OOS OOS OOS OVER FLOW Overlay Measurement The front layer and the exposure of the front layer and the level OX: SiO2 Silica PR Photo Resisit Light P1: POLY Polysilicon Pa;
Passivation passivation layer PARENT LOT Mother batch particle dust / dust particles PE: 1. Process Engineer; 2. Plasma enhance 1, process engineer 2, plasma enhancement PH: photo Huangguang or mini shadow Pilot experiment PLASMA plum POD PLYMER PLUSS PVD PP: P-Doped P - Dopase PVD Physical Voltage Deposition PW: P-Doped Well P Well Queue Time Waiting time R / C: Runcard operation card Recipe process Release release Resistance resistance RETICLE Lights RF RF RM: Remove. Ratation Rotation RTA: Rapid Thermal Anneal quickly reflator RTP: Rapid Thermal Process quickly heat treatment SA: Salicide Silicide Metal SAB: Salicide Block Silicide Metal Blind Region SAC: Sacrifice Layer Sacrifice SCRATIS Scratch SELECTIVITY Select than SEM: Scanning Electron Microscope Scanning Electron Microscope Slot Slot Source-Head Ion Source SPC Process Statistics Control Spin Rotate SPIN DRY Cyrid SPUTTER Sputtered SRO: Si Rich Oxide Oxygen Silicon Stocker Warehousing STRESS Inner Stress Strip: A Wet etching TEOS - (CH3CH2O) 4Si Tetraethylsoxysilane / orthodoxate, tetraeth ester, at room temperature. LPCVD / PECVD growth SiO2 raw materials. It also refers to the SiO2 layer that grows with TEOS. Ti TiN titanium nitride TM: TOP METAL top metal layer Tor Tool of Record Under ETCH Etching USG: undoped Silicon Glass W (Tungsten) Tungsten Wee Peripheral Exposure Yield Prime Ficd: Final CD Dicd: Development Inspection CD
Integrated circuit entry
Integrated circuit
With the development of electronic technology and the popularity of various electrical appliances, the application of integrated circuits is getting wider and wider, and the "Shenzhou No. 5" flying into the space is flying into the space. Integrated circuit.
We integrate various electronic components to the semiconductor material (mainly silicon) or insulator material, and then encapsulate it with a housing, constitute a circuit or a function of a function. system. This circuit or system with a certain function is an integrated circuit. Just as the human body consists of different organs, each organ's various organs can complement each other, and there is less than any part of any part. Any integrated circuit must work with the input port of the received signal, the output port of the transmitted signal, and the control circuit processed by the signal. Input, output (I / O) port is simple to say that we often see the socket or plug, and the control circuit is not seen, this is what the integrated circuit manufacturer is manufactured in the purification room.
If the integrated circuit is classified by integrated degree, it can be divided into small scale (SSI), medium scale (MSI), large scale (LSI) and large scale (VLSI). In recent years, the large scale integrated circuit (UISI) has a minimum design size of less than 1 um, which will have 10 million to 100 million components on each of the films.
2. System Chip (SOC)
I don't know if you have seen the American "Terminator". When watching the movie, have you ever thought that the robot can analyze a variety of problems like people, make a variety of movements, as if he also has the brain, there is also a memory. In fact, he is a system chip (SOC) at work. Of course, that is the science fiction, technology has not yet developed to that level. But SOC has become a hot spot in the field of integrated circuit design. In the near future, it can work like "Terminator". The system chip is a circuit that is less than 0.6um process size, contains one or more microprocessors (brain), and has a considerable amount of memory (used to memorize), implement a variety of circuits on a piece of chip, can work autonomously The variety of circuits here is a variety of circuits that operate on signals, just like our hands, feet, and each function. Such an integrated circuit can reuse the complicated circuit modules that have been designed, which saves a lot of time for designers.
SOC technology is widely recognized, and it is not that it has any very special features, but it can be designed in a shorter time. The main value of SOC is to effectively reduce the development cost of electronic information system products, shorten the listing cycle of the product, and enhance the market competitiveness of products.
3. Integrated circuit design
For the word "design", everyone will definitely be unfamiliar. Before building the Three Gorges Hydropower Station, we must first design it on the computer according to the location, water flow, etc. Manufacturing integrated circuits also need to design it on the computer according to the function of the required circuit.
The integrated circuit design is simple to design the hardware circuit. We will carefully think about this before doing anything to better complete this thing to achieve our expectations. We need a arrangement, a idea. When designing an integrated circuit, the designer first makes an idea based on the requirements of the circuit performance and function. This concept is then gradually refined, and an integrated circuit with these performance and functions is implemented using electronic design automation software. If we now need a fire circuit, when the temperature is higher than 50 ° C. The designer will be in accordance with our requirements, using the software to complete the design map and simulate the test. If the simulation test is successful, it can be said that the circuit we have to have.
Integrated circuit design can generally be divided into hierarchical design and structured design. The hierarchical design is to simplify the complex system, divided into one layer, which is conducive to discovering and correcting errors; structured design is partial part of the operation, allowing a designer to design only Some of them or more, such other designers can use the part of his already designed to achieve resource sharing.
4. Wilbone manufacture
We know that there are some thin slices in many electrical appliances that play an important role in electrical appliances, which are all made of silicon-based materials. The silicon wafer is manufactured for the production of the chip provides the desired silicon. So how is the silicon wafer manufactured?
The silicon wafer is cut from the large block of silicon crystals, and these large blocks of silicon crystals are refined by ordinary silicon salad. Maybe we have this experience, the block sugar will melt at the temperature high, if it is sticking to the hand, it will pull out a filament, and when the filament is pulled away from the sugar, it will hard. In fact, we have made silicon wafers here, first using this principle, merge ordinary silicon, draw large block of silicon crystals. The head and tail are then cut off, and the mechanical is used to trim to the suitable diameter. At this time, it is a "silicon bar" with a suitable diameter and a certain length. Then, "silicon rod" is then cut into a thin piece, and the thickness of the circular must be approximately equal, which is a key working in silicon manufacturing. Finally, the damage remaining when the cut is removed. At this time, a piece of perfect silicon wafer is manufactured.
5. Silicon single crystal circle
We create a chip that requires ordinary silicon to make a silicon single crystal circle, and then produce a silicon single crystal circle into a chip by a series of process steps. Let's take a look at what is a silicon single crystal circle. From the material, the main material of the silicon single crystal circle is silicon, and is a single crystal silicon; from the shape, it is circular sheet shape. The silicon single crystal wafer is the most commonly used semiconductor material, which is a state in which silicon into the chip manufacturing process is a integrated circuit raw material manufactured for chip production. It is a circular sheet fabricated through various process flows in the ultra-purified room, such a sheet must be approximately parallel and flat enough. The larger the silicon single crystal wafer, the more integrated circuits produced on the same wafer, so that it can reduce costs and improve the yield, but material technology and production technology requirements will be higher.
If the silicon single crystal circles can be divided into 4 inches, 5 inches, 6 inches, and the recent development of 12 inches and even larger specifications have also developed. Recently, the largest silicon single crystal rounded manufacturer in China is preparing to build a 12-inch wafer long line in Beijing.
6. Chip Manufacturing
With the rapid development of science and technology, the performance of chips is getting higher and higher, and the volume is getting smaller and smaller. We have no miracles created by modern technology when using various electronic products. And this miracle, do you know how is it created?
The chip is made of most common elements on the earth. Sands with ore morphology on the earth, this simple element becomes a silicon having an integrated circuit chip after an extremely unusual processing transition.
We use the circuit diagram designed on the computer to produce a mask. As light from the door, the light strip is formed on the ground, if the light and the metal film can function, the metal film is formed in the place where the film is formed, and the hole is formed in the surface of its surface, so that Making masks. We reapted the original mask on the silicon film, and the circuit diagram "Print" is "printed" on the silicon wafer by the mask. If we follow the circuit diagram to connect to the electrically conductive, it should be disconnected, so that we form the required circuit on the silicon wafer. We need multiple masks to form a circuit of the upper and lower multilayer, then the original silicon wafer is made into a chip. So we said that the silicon wafer is a raw material made of a chip, and the silicon wafer is prepared for chip manufacturing.
7.EMS
Lift EMS, you may think of postal express delivery, but the EMS in our integrated circuit industry refers to no brand products, specializing in electronic contract manufacturers produced by brand manufacturers, also known as electronic manufacturing services. Then let's take a look at what the electronic contract manufacturer is doing.
The so-called electronic contract manufacturer is to take other people's order, processing production, just like we will come back to clean your health, just do things, they must do things in accordance with our requirements. EMS has advantages in all aspects, from purchasing to production, sales or even design in design. Therefore, it became a company specializing in the manufacture of goods for brand vendors. The advantage of EMS is that its manufacturing cost is low, the reaction speed is fast, and has its own design capabilities and powerful logistics channels.
Recently, some internationally renowned EMS electronic manufacturers are moving their manufacturing base to China. Their arrivals will certainly impact companies in China. But for other companies, it may be a good news because these EMS must rely on local vendors to provide components.
8. Flow
After watching the movie "Modern Age", we may always think of the shot of Chaplin's screws. Everyone knows the same production as the water line in the film is the production line. Just as the development of science and technology, the role of Chaplin on the current production line has been replaced by the machine. We make chips through a series of process steps like a pipeline, which is the flow.
In the chip manufacturing process, there is generally two periods of time can be called a flow. When a large-scale production of chips, the water line is produced by one of them. Everyone may have known this process called the flow, but this is not as detailed below. We discovered a certain place when designing to achieve better results, but it is afraid that such modifications will bring unexpected consequences to the chip. If you have a problem-scale manufacturing chip according to such a problem, then The loss will be large. Therefore, in order to test whether the integrated circuit design is successful, the flow must be performed, that is, from a circuit diagram to a chip, check if each process step is feasible, whether the circuit has the performance and function we want. If the flow is successful, you can make a chip on a large scale; contrary, we need to find out the reasons and make the appropriate optimization design. 9. Multi-project wafer (MPW)
With the improvement of manufacturing process, the cost of manufacturing chips on the production line is rising, and the production cost of 0.6 micron process is 20-3 million, and the production cost of 0.35 micron process is required to be 60-800,000 yuan. If there is a problem in the design, then all the chips manufactured will be scrapped. In order to reduce costs, we used multi-project wafers.
The so-called multi-project wafer (simply referred to as MPW) is to design a variety of integrated circuits with the same process on the same silicon wafer, produced on the same production line, after production, each design item can get dozens of chip samples This quantity is sufficient to design the experiment and test of the design development phase. The experimental costs are shared by all the multi-project wafers assessed according to their respective chip area, which greatly reduces the experimental cost. This is very like we all want to eat chocolate, but we don't have to buy a box, you can only bought a box, then you will pay more.
Multi-project wafers have improved design efficiency, reducing development costs, providing designers with practical opportunities, and promoting the transformation of integrated circuit design results, training for IC design talents, and the development and development of new products have considerable role. .
10. Wafer
We know that SMIC International and TSMC is a well-known IT company in mainland China. The work they do is the wafer foundry. That now let us know what is wafer. We are familiar with the processing workshop, which uses various devices to send customers to wheat that require processing, rice processing into needed flour, rice, etc. This is not necessary to have people who need to process food to build a workshop. Our current wafer plant is like a processing workshop. Wafer foundry is to provide specialized manufacturing services to professional integrated circuit design companies or electronic vendors. This business model allows the integrated circuit design company to produce expensive factory buildings. This means that depression of TSMC and other wafers will be distributed to the vast products of customers and diversified products to focus on developing more advanced manufacturing processes.
With the development of semiconductor technology, the investment required for wafer founders is also growing, and now the most commonly used 8-inch production lines, the investment is set to build a $ 1 billion. Despite this, many wafer plants are still invested in many funds and purchased a lot of equipment. This is enough to show that the wafer will have greatly developed in the shortcomings, accounting for the proportion of the global semiconductor industry will increase.
11.smt
We often see there in the electrical appliance with a blockbus, there are many electronic devices. If you have the opportunity to see the back of the board, you will see the "feet" of the front device through the holes on the board to the back. There is now a new technology, which has more advantages over the perforation technology we just said.
SMT is surface mount technology, which is a new show in the electronic assembly industry. With the miniaturization of electronic products, the perforation technology that is too large, will not be suitable, and surface mount technology can only be used. It does not need to be perforated on the board but also directly on the front. Of course, the "foot" of the device is short, and it is fine. SMT makes electronic assembly getting faster and simple, so that the renewal of electronics is getting faster and faster, the price is getting lower and lower. Such a factory will be more happy to use this technique to produce quality products with low cost high production to meet customer needs and strengthen market competitiveness. The SMT has high assembly density, and the volume and weight of electronic product are only about one tenth. Usually SMT technology, the reliability of electronic products is high and strong with vibration. And SMT is easy to achieve automation, can improve production efficiency, reduce cost, which saves a large amount of energy, equipment, humanity and time.
12. Chip package
When we entered the mall, we will find that almost every item is packaged. So what is the difference between our packages and packages?
The package is the outer casing for mounting the semiconductor integrated circuit chip. Since the chip must be isolated from the outside to prevent impurities in the air to decrease the circuit performance to the corrosion of the chip circuit, the package is critical. The packaged chip is also more convenient to install and transport. These roles and packaging packaging are basically similar, but it has unique. The package not only plays, fixes, seals, protects the chip and enhancement of the performance of the circuit, but also the bridge between the internal world of the chip and the bridge on the chip to connect to the package of the package enclosure, these pins. It is also connected to other devices through the wires on the printed board. Therefore, packages play an important role in CPU and other large-scale integrated circuits. With the advancement of CPU and other large-scale circuits, the package form of integrated circuit will also have corresponding development.
The chip packaging technology has undergone several generations of changes, and the technical indicators are more and more close to 1 generation than one generation. The main indicators of the chip area and package area (the main indicators of the level of packaging technology) are getting closer to 1, and the applicable frequency is getting higher and higher. Temperature can be getting better and better. It also has the advantages of small weight, high reliability, convenient use.
13. Chip test
In order to be unbeaten in today's fierce market competition, the manufacturer of electronic products must ensure product quality. In order to ensure product quality, various types of test techniques are required in the production process, and the defects and faults are found and repaired.
When we use a chip, we often find such a phenomenon, which is not used by several of the chips. We even thought that this chip used this chip was wrong. In fact, these pins are used to test. After the chip is manufactured, the chip test engineer is also tested to the chip to see if the performance of the chip produced is in line with the requirements, whether the function of the chip can be realized. In fact, our test method is just contact testing, and there is a non-contact test in chip test technology.
With the improvement of the assembly density of the wiring board, the traditional circuit contact test has been greatly limited, and the application of non-contact test is increasingly common. The so-called non-contact test is mainly to test the chip of the manufacturing process or have been manufactured by light such substance. This seems to be a person feels the pain. He went to the hospital for a X-light perspective, see if the legs do not have fractures or other problems. This approach does not receive the impact of component density, and it is possible to find defects at a very fast test speed.
14. Crystal packaging technology
We all know that the bird cage has a space with bamboo sticks, and the birds live in this. We will have a similarities that we have to say, and the bird cage is similar. Let's take a look at what is a coating technology.
We typically form the wafer to form a front side of the circuit structure after a series of processes. The original encapsulation technology is the front surface of the wafer above the substrate is upward, and the crystal technology is in turn over, in the wafer (as seen as the plate) and the substrate (as below The block boards and the periphery of the circuit use bumps (as a bamboo stick), that is, a space is formed by a wafer, substrate, and bumps, and the circuit structure (as a bird) is in this space. . This packaged chip has the advantages of small size, high performance, short connection. With the rapid development of the semiconductor, the coating package technology is bound to be the mainstream of the package industry. A typical crystal package structure is configured by metallurgy, solder joints, metal pads under the bumps, so the consumption of metallurgical layers will seriously affect the reliability of the entire structure and the service life of the component.
15. bump process
When we were young, we often played with plasticine, and we may also play like this, just put the plasticine into a head, and then add your eyes, nose, ear, etc. And our long bumps and just mentioned "long" eyes, nose, and ear.
After the wafer is manufactured, the long bump process is performed on the wafer. After growing bumps on the wafer, we see like a pan, the edge of the pot is a bump, and the intermediate portion is used to form a circuit structure. According to the structure of the bump, it can be divided into two parts of the body and the ball metallurgy layer (UBM).
For the current wafer bump process, it can be divided into printing techniques and electroplating technology, and two technologies are all good. In terms of electroplating technology, its advantage is to provide better line width and bump flatness, providing a large chip area, and the electroplating bump technology is suitable for the characteristics of the high-lead process, and can increase the chip more Reliat, increasing the strength and operational performance of the chip. The production cost of printing technology is low and more elastic, suitable for use in large and small amounts of production, but the process control is not easy, so that this method is less applied to the production of bumps between less than 150 μm.
16. Wafer grade package
At some antique exhibitions, we often see such a situation, ie, with a glass mask in antiques. In order to air without corrosion, some methods will be sealed between the glass cover and the seat pad below. Belckouts we borrow this example to understand the wafer level package.
Wafer grade package (WLP) is a chemical bond that has been combined with a wafer (like a nigmine) on which some circuit microstructure (good bike) has another film (like glass cover) with another corroded cavity. . A protective body (silicone cap) with a sealed cavity is formed on the upper surface of these circuit microstructure, which avoids damage to the device in the process step, and also guarantees the cleaning and structural body of the wafer to be contaminated. . This method makes the microstructure in a vacuum or inert gas environment, thus improving the quality of the device.
As IC chip's functionality and high integration are increasing, the current semiconductor package industry is developing in the wafer level package. It is a common method of improving the integration of silicon wafers, with the advantages of reducing testing and package cost, reducing lead inductance, improving capacitive characteristics, improving heat dissipation channel, reducing the installation height.
17. Wafer-level chip-level packaging technology
Semiconductor packaging technology has achieved great development over the past two decades, which is expected to have more positive growth and new rounds of technological progress in the next 20 years. The chip-level packaging technology of the wafer dispensing is a very positive packaging technology that has recently appeared.
We use the ideal case of the neighboring area of the chip and the amount of the package of 1: 1, is called a chip-level package. Just like we eat oranges, always hope that its lesser is thin. The chip-level encapsulation technology of the wafer site is the chip-level package technology of the wafer position. It can effectively increase the integration of silicon. The wafer position treatment is carried out directly on the wafer, and the wafer of the same area can accommodate more chip-level chips, thereby improving the integration of silicon. Similarly, if we let people stand in a room, if we can only stand ten people in winter, and wear less in summer clothes, you can stand 11 or twelve people. The wafer-level chip-level package process will grow at a very fast speed in the next few years, which will be reflected on the mobile phone and other portable electronic devices. We will definitely have more features, such as watching TV, but they may be smaller than us, then use the wafer-level chip-level package technology.
1. Compcification Specifications: Setting the specifications of the IC, operating voltage, current, process, etc., and must consider its future test problem when designing the architecture.
2. IC Design IC Design: Designed in accordance with the specifications, the logic design and line timing are required to consider testive design and actually produce their testing. It is used for Test after IC production.
3. Compthrough circuit of the design to complete the design rules for the design rules required by the manufacturing IC, according to the design rules of the masks required for the IC.
4.Wafer Process Wafer Manufacturing: After the mask is completed, enter the wafer factory manufactured.
5.CIRCuit Probe Point Test: Use the circuit on the chip using the probe point.
6.Package Package: Decide the package of IC, the number of PINs, and packaging materials are different.
7.Final Test finished test: Function test and distinguish level.
8. Brun-in pre-feeding test: Using high temperature, accelerate the IC of reliability, early elimination.
9.Sampling Test Sampling Test: Personnel, sampling, if there is a non-good product analysis, and track the lack of the process.
10.Shipment shipments: officially listed trafficking.
