Basic knowledge of memory

- Author: Big cat - Published: 2004-11-614: 05: 41-- basic knowledge of the basics of memory RAM 1, RAM introduce some of the latest technical vocabulary CDRAM-Cached DRAM-- cache memory CVRAM-Cached VRAM - Cache Video Memory DRAM-DYNAMIC RAM - Dynamic Memory EDRAM-Enhanced DRAM - Enhanced Dynamic Memory EDO RAM-Extended Date Out Ram - Extended Data Memory EDO SRAM-Extended Date Out SRAM - Extension Extension Data Model Static Memory EDO VRAM-Extended Date Out VRAM - Extension Data Mode Video Memory FPM-FAST Page Mode - Speed ​​Page Mode FRM-Ferroelectric RAM - Ferroelectric Memory SDRAM-SYNCHRONOUS DRAM - Synchronous Dynamic Memory SRAM- Static RAM - Static Memory SVRAM-SYNCHRONOUS VRAM - Synchronous Video Memory 3D RAM-3 Dimesion RAM - 3D Video Processor Special Memory Vram-Video RAM - Video Memory WRAM-Windows RAM - Video Memory (Graphics Processing Ability Super-VRAM) MDRAM-MULTIBANK DRAM - Multi-slot Dynamic Memory SGRAM-SIGNAL RAM - Single Memory 2. What is the main technical indicator memory in memory is a device with "memory" function, which is used with two physical devices with two stable states To represent binary digital "0" and "1", such devices are called memory elements or memory units. Memory elements can be magnetic cores, semiconductor triggers, MOS circuits or capacitors, and the like. Bit (Bit) is the most basic unit of the binary number, and the minimum unit of memory storage information. The 8-bit binary number is called a byte (byte), can be formed by one byte or several bytes (Word) One or 2 bytes of one or two bytes are generally considered to be a word. Several memory cells form a storage unit, a large number of memory cells constitute a memory. In order to distinguish the storage unit in the storage, they must be numbered one by one called the address. A one or one of the address and the storage unit is a unique sign of the memory cell. Attention should be noted that the address of the storage unit and the content stored in it are completely two things. Depending on the memory in a different location in a computer, it can be divided into master memory and auxiliary memory. Inside the host, a memory or internal memory is called the memory with the CPU exchange information. During execution, the data of the program is placed in the main memory. The content of each memory cell can be referred to as a random access memory (RAM) by instruction random read-write access. Another memory is called a read-only memory (ROM), which stores one-time write programs or data, only randomly read. RAM and ROM share the address space of the main memory. After the data stored in the RAM will be lost, the data in the ROM in the power-off retaining can remain unchanged. Because of the structural, price cause, the capacity of the main memory is limited. In order to meet the required needs, large-capacity auxiliary memory or other memory, such as disk, optical disc, etc. The characteristics of the memory are described by its technical parameters. Storage capacity: The amount of binary information that memory can accommodate is called storage capacity. General main memory (memory) capacity is around dozens k to dozens of M bytes; auxiliary memory (exemplified) is at hundreds of k to a few thousand M-bytes. Access period: The two basic operations of the memory are read and written, refer to reading and writing information between the storage unit and the storage register (MDR). The memory from the received read command to the readable information stably at the output of the MDR at the output of the MDR, referred to as the number of time TA; the shortest time required between the two independent access operations is referred to as the storage period TMC. The access period of the semiconductor memory is generally 60 ns-100 ns. The reliability of the memory: The reliability of the memory is measured with the average failure time MTBF. MTBF can be understood as an average time interval between two faults. The longer MTBF, the higher the reliability, the stronger the correct work ability.

Performance price ratio: Performance mainly includes three contents of memory capacity, storage cycle, and reliability. Performance ratio is a comprehensive indicator that has different requirements for different memories. For external memory, the capacity is required, and the speed of the buffer memory is very fast, the capacity is not necessarily large. Therefore, performance / price ratio is an important indicator for evaluating the entire memory system. Can SDARM become the mainstream of the next generation of memory? Fast page mode (FPM) DRAM's golden era has passed. With the support of the Efficient memory integrated circuit and the support of core logic chipsets such as Intel HX, VX, which optimizes Pentium chip running efficiency, people are increasingly tend to adopt extended data output (EDO) DRAM. The EDO DRAM uses a special memory readout circuit control logic, and when reading and writing an address unit, the read and write cycle of the next continuous address unit is started simultaneously. Thus, the time of reselection addresses, enhances the rate of storage bus to 40MHz. That is to say, memory performance has increased by nearly 15% to 30% compared to fast page memory, and its manufacturing cost is similar to the fast page memory. However, EDO memory can only be brilliant, and its time to dominate the market will be extremely short. Soon after the market, the main frequency of the mainstream CPU will be up to 200MHz. To optimize processor operation, the bus clock frequency is at least 66 MHz. Multimedia applications and Windows 95 and Windows NT operating systems have become higher and higher, in order to mitigate bottlenecks, only new memory structures to support high-speed bus clock frequencies, not inserted into the instruction waits cycle. In this way, in order to adapt to the needs of the next generation of mainstream CPUs, theoretical speed can be synchronized with the CPU frequency, with the CPU sharing a clock cycle, SDRAM (Note and used as the SRAM difference used as Cache, SRAM full-write It is static ram, but the speed is fast, but the cost is high, it is not suitable for the main memory. It will become the mainstream of memory development compared to other memory structures. SDRAM is based on a dual storage structure, contains two interleaved storage arrays, and the other is ready to read and write data when the CPU is accessing data from a bank or array. The read efficiency is doubled by the tight switching of the two storage arrays. The maximum speed of SDRAM in last year can reach 100MHz, synchronized with the mid-range Pentium, and the storage time is as high as 5 ~ 8ns, and Pentium system performance can be increased by 140%, and each of the Pentium 100, 133, 166 can only improve performance a few percent. The ten CPUs seem to be a smart upgrade strategy compared to SDRAM. Many DRAM manufacturers last year have started listing 4MB × 4 and 2MB × 8 of 16MB SDRAM memory strips, but their cost is higher. Now every memory manufacturer is expanding the SDRAM production line. It is expected that the SDRAM will dominate with a large number of 64m SDRAM memory sticks in early 1998. Its price will also drop sharply. However, there are still many difficulties in the development of SDRAM to overcome, one of which is the limitations of the core logic chipset of the motherboard. The VX chipset has begun to support 168 line SDRAM, but only one 168 line memory slot is only 32M SDRAM, while the Simple and efficient HX motherboard does not support SDRAM. The next-generation Pentium motherboard chipset TX will make better support SDRAM. Intel's latest next-generation Pentium motherboard chipset TX will better support SDRAM. SDRAM can be used not only for the main memory, but also has a wide range of applications for private memory. For the display card, the wider the data bandwidth, the more data processing, the more information displayed, the higher the display quality.

Previously, a dual port video memory (VRAM) that can be readily read and written, but this memory cost is high, the application is greatly limited. Therefore, in a general display card, inexpensive DRAM and efficient EDO DRAM applications are wide. However, with the listing of 64-bit display cards, the bandwidth has been expanded to the limit of the bandwidth that the EDO DRAM can achieve, to achieve a higher 1600 × 1200 resolution, and try to reduce costs, only the frequency is 66MHz, High bandwidth SDRAM. SDRAM will also be applied to shared memory structure (UMA) - an integrated main memory and display memory. This structure has largely reduced system cost, because many high-performance display cards are high, because their dedicated display is extremely high, and UMA technology will use the main memory to display memory, no longer need to add special display memory. It is therefore reduced. What is Flash Memory Memory Introduction to Flash Memory Related Knowledge In recent years, new semiconductor memories develop quickly are flash memory. Its main feature is to keep the stored information for a long time without power-on. For its essence, Flash Memory belongs to the EEPROM (Electric Erasure Programmable Read-only Memory). It has the characteristics of ROM, but also high access speed, and easy to erase and rewritten, small power consumption. At present, its integration has reached 4MB, and the price also has declined. Because Flash Memory's unique advantages, if you use Flash Rom BIOS on some newer motherboards, it will make BIOS upgrades are very convenient. Flash Memory can be used as a solid-state large capacity memory. The large-capacity memory currently used is still a hard disk. Although the hard disk has the advantages of large capacity and low price, it is electromechanical equipment, mechanical wear, reliability and durability relatively poor, anti-impact, weak anti-vibration power, and power consumption. Therefore, I have always wanted to find the means of replacing the hard disk. Because the Flash Memory integration continues to increase, the price is reduced, which makes it possible to replace small capacity hard drives on the portable. The Flash Memory, which is currently developed, is compliant with the PCMCIA standard, which can be easily used in a variety of portable computers to replace disks. There are currently two types of PCMCIA cards, one called Flash memory card, which only the Flash Memory chip consists of only the Flash Memory chip, and special software is required to manage. Another kind of Flash drive card, which except for the Flash chip, in addition to the Flash chip, a control circuit consisting of a microprocessor and other logic circuits. They are compatible with IDE standards and can be done as in DOS. Therefore, they often refer to them as Flash Solid Masses. Flash Memory is still not big enough, and the price is not cheap enough. Therefore, it is mainly used in a portable system that requires high reliability, light weight, but large capacity. The BIOS system has rested in the Flash memory in the 586 microcomputer. What is Shadow Ram Memory Shadow RAM, also known as "shadow" memory. It is a special technology to improve system efficiency. The physical chip used by Shadow RAM is still a CMOS DRAM (dynamic random access memory) chip. Shadow RAM occupies a part of the address space of the system's main memory. Its address is c0000 ~ ffffff, which is 768kb ~ 1024kb area in the 1MB main memory. This area is often also referred to as a memory reserved area, and the user program cannot access directly. The function of Shadow Ram is used to store content of various ROM BIOS. Or say the content in Shadow Ram is the copy of the ROM BIOS. Therefore, it is also called ROM Shadow (ie, the content of Shadow Ram is "shadow" of the ROM BIOS). When power is powered on the machine, the system BIOS will automatically display the BIOS of the BIOS and other adapters to the specified area of ​​the Shadow RAM.

Since the physical addressing of the Shadow RAM is the same as the corresponding ROM, simply access the SHADOW RAM when you need to access the BIOS, without having to access the ROM. Usually the time of the ROM is about 200 ns, and the time to access the DRAM is less than 100 ns (the latest DRAM chip access time is about 60 ns or less). During the system run, the data module read in the BIOS or the program module in the BIOS is quite frequent. Obviously, after shadow technology, it will greatly improve the working efficiency of the system. Press the button You can see the address space allocation diagram, in the 1MB main memory space shown in the figure, the area below 640KB is regular memory. The 640kb ~ 768kb area is preserved as a display buffer. The 768kb ~ 1024kb area is the Shadow RAM area. In the system settings, this area is divided into blocks in size of 16KB size, and is allowed by the user to set it. C0000 ~ C7FFF These two 16kb blocks (total 32KB) are often used as the Shadow area of ​​the ROM BIOS of the card. C8000 ~ Effff These 10 16KB blocks can be used as the Shadow area of ​​the ROM BIOS of other adapters. F0000 ~ fffff A total of 64KB is specified by the system ROM BIOS. It should be noted that Shadow Ram can only be used when the system is configured with more than 640KB or more. When the system memory is greater than 640KB, the user can set the memory in the CMOS settings to "Allow" (enabled) to "Allow" in the CMOS settings. What is EDO RAM memory is one of the most important components in your computer. Since the birth of the microcomputer, its heart-CPU has changed its replacement, which has developed to PentiumII, compared with the original, it has two magnitude growth in the speed. Memory constituent devices RAM (random memory) - generally DRAM (dynamic random memory), although the capacity of a single chip is constantly expanding, but the access speed is not much improved. Although people have used high-speed but expensive SRAM chips to increase a buffer device between CPU and memory, the speed does not match the speed between the two. But this does not solve the problem at all. So people concentrate on the DRAM interface (on the way of sending and receiving data). In the RAM chip, except for storage units, there are some additional logic circuits. Now, in addition, the additional logic circuit of the RAM chip can increase the data traffic within the unit time by increasing a small amount of additional logic circuitry. The so-called increase bandwidth. EDO has made an attempt in this respect. Extended Data Out - EDO, sometimes referred to as a hyper-page mode - Hyper-page-mode) DRAM, and burst EDO (Bust Edo-Bedo) DRAM is two-page-mode memory-based memory technology . The EDO has been introduced into the mainstream PC approximately a year ago, which has become the main memory selection of many system vendors later. Bedo is relatively updated, and the attraction of the market has not yet reached the level of EDO. EDO work is quite similar to FPM DRAM: first trigger a row in memory, then trigger the required column. However, when the information you want, the EDO DRAM does not turn the column into non-contact state and turn off the output buffer (which is the way to take the FPM DRAM), but is kept open by the output data buffer until the next column. Access or the next read cycle begins. Since the buffer remains open, EDO eliminates the waiting state, and the burst transmission is more rapid. EDO also has a faster ideal burst read cycle clock than the 6-3-3-3 of FPM DRAM: 6-2-2-2. This allows 3 clock cycles that can save 3 clock cycles from DRAMs from DRAM on a 66 MHz bus. EDO is easy to implement, and there is no difference between EDO and FPM on the price, so there is no reason not to choose EDO.

BEDO DRAM can improve the FPM clock cycle than EDO. Since most PC applications access memory in a four-week burst, fill the cache memory (system memory to populate data to the L2 cache, if there is no L2 cache, populate the CPU), so once you know the first one Address, the next three can be available quickly by DRAM. BEDO's most essential improvement is an address counter to track the next address on the chip. BEDO also adds the pipeline level, allowing page access cycles to be divided into two parts. For internal memory operation, the first part is responsible for reading data from memory arrays to the output stage (second-stage latch), and the second part is responsible for driving the data bus to the corresponding logic level from this latch. Since the data is already in the output buffer, the access time is shortened. Bedo's maximum burst clock is scheduled to be 5-1-1-1 (using 52nsbedo and 66-MHz bus) than optimized EDO memory, saving four clock cycles. How is the actual memory structure that works is arranged in a matrix form by many basic storage units and adds logic circuits such as address selection and read / write control. When the CPU is to read data from the memory, a number of addresses is selected and the content stored on the store is stored on the content stored. Early DRAM's storage speed is slow, but with the rapid development of memory technology, a DRAM technology called fast page mode is then developed, called FPDRAM. The read period of the FPM memory starts from the trigger of a row in the DRAM array, then moves to the first column of the position indicated by the memory address and triggered, which contains the required data. The first information needs to be confirmed whether it is valid, then the data needs to be saved to the system. Once the first correct information is found, the column is changed to a non-contact state, and is prepared for the next cycle. This introduces a "waiting state" because there is no matter what happens when the column is non-contact state (the CPU must wait for the memory to complete one cycle). Until the next cycle start or the next message is requested, the data output buffer is turned off. In the fast page mode, the next column of the data is triggered when the position placed in the desired next data is predicted. The trigger of the next column only has a good effect when it performs sequential read operations on the memory. Reading from 50 nanosecond FPM memory, ideal case is a burst cycle arranged in the form of 6-3-3-3 (6 clock cycles for reading the first data element, next) Each 3 clock cycles are used for 3 data elements behind. The first stage contains the additional clock cycle required to read trigger rows. Once the ranks are triggered, the memory can be transmitted with the speed of 3 clock cycles per data. Although fp ram has improved, it still does not keep up with new high-speed CPUs. A new high-speed memory chip such as EDO RAM and SDRAM quickly appeared. This section describes how to cache the processor cache, usually refers to the Level 2 cache, or an external cache. The L2 cache has always been a type of memory that is very fast and the price is also expensive, called SRAM (static RAM), is used to store data frequently used by CPUs so that the CPU does not have to rely on slower DRAM. The simplest form of SRAM uses asynchronous design, that is, the CPU sends the address to the cache, finds this address by the cache, and then returns the data. At the beginning of each visit, you need to extends an additional clock cycle to find the characteristic bit. In this way, the fastest response time that the asynchronous cache can achieve is from 3 to 2-2-2-2, and usually only 4-2-2-2-2. The synchronization cache is used to cache the delivered address to assign the process of finding the address to two or more clock cycles. SRAM stores the requested address in a register within the first clock cycle. In the second clock cycle, the SRAM transmits the data to the CPU. Since the address has been saved in a register, the next synchronization SRAM can receive the next data address at the same time on the CPU reads the previous request.

Thus, synchronous SRAM can receive and decode the additional address from the chipset to "discharge" continuous data elements. Optimized response time can be reduced from 2-1-1-1 on the 66MHz bus. Another type of synchronous SRAM is called pipelined burst. The pipeline is actually an output stage to cache data read from the memory address, so that it is possible to quickly access the continuous data read from the memory, and save the memory array to obtain the next data element. delay. The pipeline is the most efficient access mode such as a linefill of the cache. What is ECC memory ECC is an abbreviation for ERROR CORRECTION CODING or ERROR Cheching and Correcting, which represents memory with automatic error correction. The current ECC memory generally only corrects an error in one binary number. Intel's 82430HX chipset supports ECC memory, so the motherboard with 82430HX chip can generally be installed using ECC memory. Since the ECC memory cost is relatively high, it is mainly used in a commercial computer that requires a relatively high reliability of the system. Since the case where the memory error does not occur frequently, the general home computer does not have to use ECC memory, and there are many control circuit chips that cannot support ECC memory, so many hosts should not install ECC memory, users should pay attention to ECC memory does not blindly. Can SDRAM mix with EDO RAM? SDRAM is a new generation of dynamic memory, also known as synchronous dynamic memory or synchronous DRAM. It can use the same clock with the CPU bus, while EDO and FPM memory are asynchronous with the CPU bus. At present, the read and write cycle of the SDRAM memory is generally 5-1-1-1. In contrast, the EDO memory is generally 6-2-2-2. That is, the read and write cycle of SDRAM is 4% more than EDO, which is about 28% of memory read and write time, but actually due to the constraints of other devices within the computer, computer using SDRAM can increase performance 5 to 10%. Although there are many hosts support SDRAM and EDO memory hybrid installation, it is best not to mix. The reason is that most SDRAM can only work at 3.3V, while the EDO memory is mostly working at 5V. Although the DIMM and SIMM are powered on DIMM and SIMM, their data lines are always connected. If SIMM (72-wire memory) is mixed with DIMM (168 line SDRAM), although the system can work normally, it may be After using a period of time, the data input of the SDRAM will be damaged. Of course, if your SDRAM is a product of width voltage (3V ~ 5V), there will be no such damage. At present, some SDRAM products of T1 and Sumsung support to wide voltage mode, which can be mixed with EDO memory. Cache - Cache Introduction CACHE Raise With the speed of the CPU, it often needs to be inserted when working with the dynamic memory DRAM, which is difficult to play the high speed of the CPU, and it is difficult to improve the performance of the whole machine. If a static memory is used, it can solve this problem, but the SRAM is high. Under the same capacity, the price of SARM is 4 times the DRAM. Moreover, the SRAM is large and the integration is low. In order to solve this problem, a cache-Cache technology is used in the motherboard above 386DX. The basic idea is to use a small amount of SRAM as a buffer between the CPU and the DRAM storage system, that is, the Cache system. A significant feature of 80486 and higher microprocessors is that SRAM is integrated into the processor chip as Cache, and since these Cache are mounted in the chip, it is called Cache. The capacity of Cache in the 486 chip is usually 8K. High-grade chip such as Pentium is 16KB, Power PC up to 32KB.

The Pentium microprocessor further improves Cache in the film, using data and dual channel Cache technology, relatively, in-chip Cache has little capacity, but very flexible, convenient, greatly improves the performance of the microprocessor. The in-chip Cache is also known as the first-class Cache. Since the clock frequency of the 486, 586 and other high-end processors is high, the performance will be significantly deteriorated once the first-level cache misses. In this case, the method uses to add Cache in addition to the processor chip, called secondary Cache. The second-stage Cache is actually true buffering between the CPU and the main memory. Since the response time on the system board is much lower than the speed of the CPU, if there is no secondary Cache, it is impossible to reach the ideal speed of high-end processors such as 486, 586. The capacity of secondary Cache is usually more than one level of Cache. In system settings, the user often requires the user to determine if the secondary Cache is installed and the size is equal. The size of the secondary Cache is generally 128kb, 256kb or 512 kB. In 486 microcomputers, 256 kB or 512KB synchronous cache is generally employed. The so-called synchronization means that the Cache and the CPU use the same clock cycle to operate in the same speed. Performance can be increased by more than 30% relative to asynchronous Cache. What is the Cache memory called Cache, ie, a cache, is a smaller but velocity of memory between the CPU and the main memory DRAM (Dynamic RAM), typically consisting of SRAM. SRAM (Static RAM) is an English abbreviation for static memory. Since the SRAM uses the same semiconductor process with the production of CPUs, the SRAM has a fast access rate, but the volume is large, and the price is high. Since the read and write speed of the main memory composed of dynamic RAM is lower than the speed of the CPU, and the CPU has access to one or more main memory each executed, the CPU is always in the waiting state, and it has severely reduces the efficiency of the system. After cache, some copies of the main memory content are stored in Cache, and the CPU will first access Cache when reading and writing data. Since the speed of Cache is comparable to the CPU, the CPU can quickly complete the data read and write in the zero-waiting state. The CPU is going to access the main existed only when the data required for the CACHE is not included. The CPU finds the desired data name when visiting the cache, otherwise it is called no missed. Therefore, the hit rate of accessing Cache has become the key to improving efficiency. Increasing the hit rate depends on a series of factors such as the image form of the Cache memory and the algorithm of the Cache content. When expansion of memory expansion, which rules should be followed when the memory expansion capacity should follow some of the following rules: 1. For most PCs, you cannot be in the same group (each group includes two to four outlets) will be different. SIMM strips are mixed together. Many PCs can install different capacity SIMMs, but all SIMMs mounted in the same group of PCs must have the same capacity, for example, for a four-slot group, the PC generally accepts 1MB SIMM strip. 4MB SIMM strips can also be accepted, and 1MB SIMM can be installed in each slot of the group, this group can accommodate 4MB of memory. 4MB SIMM can also be installed in each of the groups, and this group can accommodate 16MB of memory. However, a 1MB SIMM strip cannot be inserted into two slots in two slots in two slots, and inserting 4MB SIMM strips in the other two slots. 2. For many PCs, if different speeds of SIMM are mixed, even if their capacity will bring trouble. For example, a 4MB memory that has already runs 60 nanoseconds (Ns) in your computer, and the SIMM of 70ns can also work in the document. If a SIMM strip is re-inserted in the idle memory slot of the motherboard, the machine will refuse guidance or it will be trapped in the collapse after starting.

For some machines, if the low speed of the SIMM is placed in the first group, the speed mixing problem can be resolved. The computer will be accessed at the lowest speed, and the remaining portion will not be useful. 3. For most PCs, all slots of a group must be inserted. Or put a set of full space (of course, the first group is not line). You cannot only be partially installed in a group. 4. The SIMM size acceptable by the PC has a limit (maximum value can be found in the PC manual. If there is no manual, the only method is to find the maximum value from the practice). What is a 30-wire, 72 line, 168 line memory module, 30-line; 72 line; 168 line introduction, 3 lines, 72 lines, 168 lines of memory sticks related to knowledge and mutual distinguishing stroke memory is some memory chip Soldering is made on a small punching circuit board, namely the memory strip, the number of memory strips is the number of pins, and the memory strips can be divided into 30-wire memory strips, 72 lines according to the number of pins. Memory strips (SIMM, SIGLE Inline Memory Modle) and 168-wire memory sticks (DIMM, Double Inline Memory Module). The number of pins of the memory module must match the number of pins of the memory slots on the motherboard, and the memory strip slot also has three types of 30 lines, 72 lines and 168 lines. The 30-line memory module provides 8-bit valid data bits. Common capacities have 256 kB, 1MB, and 4MB. The volume of the 72 line is slightly large, and 32-bit valid data bits are available. Common capacity has 4MB, 8MB, 16MB and 32MB. Press the button You can see the appearance of the 72-line memory module. The 168-wire memory bar is large, providing 64-bit valid data bits.

- Author: Big cat - Published: 2004-11-614: 06: 11-- Memory Basics (continued) How to identify Cache memory chip mark the current computer system, commonly used in static RAM capacity has 8K × 8 Bit (64kbit), 32K × 8 (256kbit) and a 64K × 8 (512kbit) of three chips, access time (cycle) is 15ns to 30ns. The above parameters are often marked on the static SRAM chip: XX64-25 (XX65-25), XX256-15 (XX257-15), XX512-15, etc. Take XX256-15 as an example, "256" indicates that the capacity (unit is kbit), "15" indicates the access time (in ns). In the numerical value indicating the SRAM memory capacity, "64" is the same as "65", which represents the capacity of the chip to 64kbit, ie 8kb. Similarly, "256" and "257" have the same meaning, that is, the capacity of the chip is 32 kB. For example, the SRAM chip used on the ASUS PVI686SP3 motherboard is W24257AK-15, ie the chip has a capacity of 32K × 8 bits, and the access speed is 15ns. How to detect cache in software? Detection; cache introduction; Cache introduces software to detect Cache's method The size of the Cache on the motherboard and is difficult to use the general method, especially if some motherboard connects BIOS to be modified by the illegal dealer. 486 The commonly used pull-down method is now inadvertently - a lot of cache chips on the Pentium motherboard are directly SMT (surface mount), and cannot be plugged. Testing Cache software does have some, such as CCT, but ordinary users are rare to these professional software. What is memory? The least memory physical unit is bit, from essentially, the bit is an electrical unit located at a certain binary state (usually 0 and 1). The eight-bit constitutes a byte, which may have 256 species (2 8 times). Bytes are the minimum unit of memory accessible, each such a combination, can represent a separate data character or instruction. The ASCII code character set actually only uses 7 bits, so support 128 possible characters. This number is complete enough for all 26 English letters (including case), numbers and special characters. The number of characters in certain languages ​​is large, so they may use the "double word" character set (such as Chinese characters). The memory used on the PC can be divided into two categories, namely read-only memory (ROM), respectively, access memory (RAM). As can be seen from their name, the ROM data cannot be updated casually, but it can be read at any time. Even if it is power-off, the ROM can also retain data. As for RAM, you can read and write at any time, so RAM is usually used as a temporary storage medium (which can be called system memory) for operating systems or other running programs. Unfortunately, the RAM cannot retain data when power-down, and if you need to save the data, you must write them into a long-term memory (eg hard drive). Because of this, the RAM is sometimes referred to as "variable memory". RAM memory can be further divided into two categories: static RAM (SRAM) and Dynamic Memory (DRAM). Dram is slower than SRAM due to differences in realization. SRAM consists of a logic transistor, and the data is stored in a trigger. Therefore, the speed of change and reading the memory cells is very fast. And DRAM uses capacitance to store data. Since the capacitor is gradually discharged, it must be recharged periodically (ie: refresh). Since the capacitance is also discharged during execution of the read operation, it must be recharged after each read operation.

Refreshing operations requires a clock cycle, which may affect other operations. Although SRAM is more than 10 times faster than DRAM, it is much more expensive than Dram - in fact, SRAM is 10 times more than DRAM. Memory uses the ROM memory to save the BIOS program on the PC is ideal, and the latter is a basic boot program. This boot process is very small and can reside in less memory (less than 2MB). ROM memory includes programmable ROM (PROM), erasable programmable ROM (EPROM), erasable programmable ROM (EEPROM), etc. At present, BIOS is generally used by EEPROM, because it can be rewritten by power-on, thereby enable program upgrade to the BIOS, thereby placing a new boot program in the chip. This is the so-called "Flash BIOS". The initial microcomputer is designed toward the low-cost low-end direction, and the cost of its components is also very low, and the system memory has always been using low-cost (so slowly) DRAM. When the PC occurs, the speed of the DRAM is sufficient to handle the bus speed of 8086/8088 4.77MHz, even in a faster 80286 processor (bus speed up to 12MHz, or 80ns). As 80386 appears, the clock speed can reach 20 MHz, 25MHz, or even 33MHz, the existing DRAM does not meet the speed requirements. In order to eliminate inconsistencies between the processor and the main memory, the designers began to use a small amount of SRAM memory on the motherboard, and they run at the system bus speed to save the most recent data. Although the speed of SRAM is much faster than DRAM, the speed of the processor has exceeded the speed of the motherboard cache again. When 80486 appears, the interior of the chip has been placed in an 8K SRAM cache because it is running at the CPU speed, thus referred to as a first layer (L1) cache, and the cache on the motherboard is referred to as L2. Today's high-performance system is still in this "memory hierarchy". Memory is worth paying attention to all DRAM basic kernels, so the internal speed is also the same, while the waiting time is relatively relatively large. In the past few years, many programs have been designed to optimize or eliminate these limitations, but the results are often improved in an aspect, and in another aspect is not as good as before. Since the cost of SRAM is relatively high, the competition in the industry is quite intense, so DRAM is still a very viable option of mass memory memory, including in the graphic subsystem. SRAM memory is usually only used as a cache: external cache (on the motherboard) or an internal cache (built into a very small part of the processor or DRAM chip). The development speed of the processor's frequency is quite amazing, so the memory designer has to greatly increase the speed of DRAM without significantly improve its cost. If the processor takes more than one clock cycle to execute an instruction, the memory subsystem can operate at a speed of 2 to three times, then the memory is also coordinated with the CPU speed. As the processor performance is getting excellent, one or even multiple instructions can already be performed within a clock cycle. Unfortunately, although the current speed of the processor can reach 500 MHz, the speed of the main memory is limited to 100MHz (133 MHz may reach in some cases). At this time, the speed between memory and processors has an offset. The main reason for this disorder is that the main memory usually uses DRAM, which is too slow. Many methods for designing SRAM and DRAM are proposed and implemented. Each method is desirable to solve the speed problem in a certain situation. However, unfortunately, we have not found a "ideal" memory architecture to solve all problems.

Because anyone has no significant increase in the speed of DRAM without significant improvement of its cost. The current development direction processor is still growing rapidly. About 2000 mainstream processors will reach 1GHz. The memory that is currently in use will soon appear too slow, and of course, new design will be available soon. In the past few years, people have put forward many design programs, but they or abandoned due to marketing and corporate policies, or are limited to small applications. SRAM and DRAM memory have experienced a gradually evolved process, from single-chip, asynchronous, single-row structure to multi-chip, synchronous multi-row structure, and more advanced technologies, such as pipeline operation, pulse mode access, Data prefetch. Also design dedicated DRAM is designed specifically for graphics, communication, and other applications. One thing seems to be determined - processors and memory will gradually become more cheap, and life cycles will be relatively short. Eventually we may see such a situation: not only the L2 cache is embedded in the chip, but the entire system RAM is also embedded. Because the DRAM can run, or close to the processor speed, there is no need to use the SRAM cache. The upgrade of memory is also the upgrade of the processor, however the total price is still maintained at a relatively low level. The memory subsystem PC consists of several basic parts: central processing units, memory subsystems, I / O subsystems, may also include a graphic subsystem. In the discussion on how to improve computer performance, most of them focus on how to improve the speed of the CPU, and ignore other aspects. Although the speed of increasing the CPU does increase the performance of the system to a certain extent, it is also an incomingible problem from the main memory. The memory controller is between the CPU and I / O subsystems (including graphic subsystems). You may be (correctly) guessed that all data must pass through - no matter where they are entering or leaving the processor. If the processor must wait for the memory subsystem to send or write data, the processor's clock cycle will be wasted, thereby reducing the total performance of the system. For the illustrative description, we can examine a system with a CPU speed of 500 MHz and an SDRAM speed of 100 MHz. For simplicity, we assume that one instruction can be performed in each clock cycle, and the memory can be sent / received during each clock cycle. At the same time, it is not considered that other operations that require CPU deduplication may occur. In this simple example, the CPU can process 500 million instructions (and / or data) per second, and the memory can only transfer 100 million data per second. The result is that there are 4 waste on every 5 CPU clock cycles. Even if the CPU may deal with some interrupts, control some I / O operations, but still have a lot of time to waste on the waiting data. Although there have been (or can develop) high-speed memory to overcome this problem, their cost is often too high on PC. When considering this problem solution, designers must fully consider possible additional costs and consider whether consumers are willing to add this cost. Because of this, many advanced technologies have been ignored, and those performance acceptable but have a lot of designs that have low cost. It is much more complicated to improve performance than the previous example. Despite this, we can still feel the speed of the processor far exceeding the DRAM memory. Add a small amount of SRAM cache in memory helps eliminate the problem of mismatch. Over time, the cache increases from the initial several KB to 2MB cache on the desktop system. Some high-priced server systems even include more caches, for them, the price is not the most important consideration. The cache is a very important temporary storage area to save a small amount of data bits, which are "near" relative to the CPU. The basic principles of cache theory are so-called time and space localities.

The time is simple to say that the data that has been accessed quickly has been accessed quickly, and the space is localized in the space, the next accessible data area will be close to the data that is just accessed. We can use a law firm to make an alteration, here, the documents are generally placed in the file cabinet. When a case is to be processed, all case files may be taken and put them in a lawyer's briefcase. So all related documents are "reached" (spatial locality). In research, there may be many files to be reviewed multiple times (time locality). Compared to this, if the lawyer is going to the file cabinet every time you need a file - this will spend a lot of time. For most applications, the use of cache is very good, and the study also shows that the cache can meet the CPU 98% of data requests during normal operation. Unfortunately, as the processor speed is further improved, mainstream applications become bigger and bigger, we have to constantly modify or adjust the cache used. In fact, the use of cache theory has reached the limit, and we will discuss this in this article. To a certain extent, simply add more cache (or more cache hierarchical) will reach a revenue decrement point sooner or later, it is likely to begin to reduce system performance. Or use the previous class ratio, if you are not one or two case files in the briefcase of the lawyer, but 40 or 50, you will find problems still exist. Some applications have a very large working set, even more than 2MB cache, and SSE in the instruction set will completely ignore the cache. At this time, other methods must be used to quickly read data from the DRAM and / or SRAM. The bus speed of the system's bus speed system is the speed of DRAM and CPU communication, which may also become a bottleneck problem that restricts the high speed of the system. The basic methods of initially improve system performance are aimed at it. In fact, the bus speed increases from 4.77 MHz to 33MHz (from 8088 to 80386) before using the cache technology. Although the speed of the processor is also growing rapidly, at the time, the speed of DRAM is sufficient enough to match the speed of the CPU. Although the initial 80486 processor speeds only 25MHz and 33MHz, but the speed will soon reach 50MHz, 66MHz, 100MHz or even 133MHz. Slow DRAM speed limits the bus speed under maximum of 50 MHz. This means that the processor has to double, triple, or four times the frequency division clock to achieve faster speed, because there are two or three CPU clock cycles in each memory clock cycle, so that the speed is obvious. Mismatch. The SRAM cache is used as an important part of the system design. The Pentium processor uses the over-scale architecture, and multiple instructions can be performed during each cycle. At the same time, the bus speed of the system has increased to 60MHz, then increased to 66MHz. This makes the demand for fast DRAM more urgent. With the rapid development of technology, the processor has exceeded 200MHz, and the CPU had to use 3X or even more multiplier factors. The bus speed of the system is constantly increasing, first increasing to 75MHz (earliest use on the Cyrix processor) and then increased to 100MHz. Soon, it was increased to 133MHz. We can further increase the speed of the bus. The bandwidth bandwidth substantially refers to the maximum amount of data that can be sent within a given time. The size of the bandwidth can be obtained by multiplying the bus width through the bus speed. The bus width refers to the number of data bits that can be transmitted at the same time. You can regard the bus width as the number of lanes on the system highway. The bus width can be doubled to increase the amount of data transmission and the bus speed is not used. Early IBM PC (8086) The bus width of 8 digits was increased to 16 bits when PC AT (80286). Soon on 80386 to 32 digits.

When the Pentium? Processor appears, it has increased to 64 bits and is still using the 64-bit bus width. From 8 to 64-bit evolution, as well as the growth of bus speeds, it is to improve bandwidth. Intel? In Pentium? PRO (and later) uses a dual independent bus design to move the L2 cache to its own bus, thereby greatly improves bandwidth, which is the so-called back bus. Theoretically, the processor can handle the size equal to the clock speed multiplied by all the data of the bus width. This means that a 233MHz processor having a memory bus width of 64 bits can reach 1.8GB / sec at an ideal case of 1.8GB / sec, but 66MHz system bus limits limit the bandwidth to 533MB / sec. The only way to enable the data rate to reach the processor acceptable range to improve the bus speed of the memory so that it is equal to the speed of the processor. However, in practical applications, only those high-load multitasking multi-user systems need to use all bandwidth. Most desktop systems are even rarely used by 50% of available bandwidth. The particle size particle size is the minimum value of the system memory expansion increment. It must be small enough so that the initial cost can be maintained at a lower level, but it must also be large enough to support reasonable expansion. As the bus width is increased, the particle size has gradually become an important issue. For the same chip manufacturing process, the double bus width means double the number of chips - the size of the memory is also doubled. The result is that the number of modules is larger than the user's needs, so they either have to use smaller memory, either use more memory than they actually need. Fortunately, this problem seems to be compared to the price because the price is low. There are very few home PCs that will be installed 64MB or more memory. Waiting cycle waiting cycle refers to the number of clock cycles that have received the data after starting the data request. The latch and decoding, queue exchange, and the sending data to the output buffer will affect the wait cycle of the DRAM. When you first access the DRAM chip, even two to three cycles are required to set the chip. I know this very critical for applications that require a lot of random memory access. Many DRAM operations are optimized to eliminate the waiting cycle after the first visit, rather than decently reduced waiting cycles. Although most designers (especially Intel) are mainly concerned with bandwidth, the waiting cycle is increasingly becoming an important bottleneck problem affecting system average performance. The reality is that when the band is knocked up 1000, the DRAM waits may only turn over eight. The main reason for waiting cycle issues is neglected is cost problem. Increasing bandwidth and access SRAM caching is two ways to improve performance relatively inexpensive. Unfortunately, most "cheap" improvements have been exhausted, which means that there is a high cost to improve performance, or only a limited performance increase - unless some new breakthroughs have occurred. The intellectual point of memory is increasingly becoming more and more, and the memory subsystem has become an important performance bottleneck as the processor is getting faster. The system and memory designers continue to use some ways to develop the memory speed to keep up the CPU development speed while maintaining a lower cost. In this regard, two methods for increasing the bus speed and add a small amount of SRAM caching have been successful, but they are only one aspect of specific practices. In the past few years, memory has also been greatly improved, although it is not as good as the processor progresses. In the following article, we will explore how to improve SRAM and DRAM to improve speed and optimization system performance. - Author: Wind commitment - Published: 2004-12-1714: 46: 52-- powerful ~~ !!!

- Author: dal686-- Published: 2004-12-17 19: 34: 42-- ooooooooooooooookkkkkkkkkkkkkkkkkkkkk