Written in front
Studying Verilog HDL has some time, at this time, at this time, from this point, do not understand the beginning of learning, mainly to see Xia Yuxong's entry of this book - "Verilog Digital System Design Tutorial", Writing is particularly good. Then look at some of the information, learning language, learning software. But I haven't done anything in the past year, I have two basic development boards, have compiled some small procedures, and there is nothing wrong with the real app. However, there are a lot of experience in the process of learning, I feel that the harvest is not small.
I think the design of the digital circuit is not only to learn the language, but also have a certain hardware foundation, such as the basic circuit design, the basic knowledge of the digital circuit, anyway, the surface involved is still relatively wide. If the foundation is not good, I don't want it. I am also the same. The things that college students are basically forgotten. But when I use it, I will try it again.
These things are not to express anything, nor, what is the specific length of you, how high is the matter, I have a summary of myself. Because I think a lot of masters will provide the beginners to provide such a entry, I also understand the feelings of beginners need to get into the entrance, so there will be this thing. Since my own level is also very limited, I can't provide a special high-profile theory and method. I hope everyone will not yet me, and my time is also more nervous. This thing doesn't know what progress will be written. I hope someone Pay attention, some people provide comments and suggestions, some people come to help me. In addition, some things are also copying the teacher. I hope that Xia Teacher will see you don't sue me. I have no business purposes, just to summarize myself, give some opinions and suggestions for later people. If you want to learn better, I think I should buy the book of this summer. I bought this pricing 38 yuan, Beijing University of Aeronautics and Astronautics Publishing, Xia Yu Wen, the title is "Verilog Digital System Design Tutorial" .
While learning language, I think it should be to learn hardware, after all, we are to design hardware circuits to learn. I use Altera's CPLD and FPGA, both have made a basic development board, which is to do the download, crystal, reset button, and power these things. All Io ports are taken out, you can insert On the user board, you can also use the oscilloscope, logical tester and other equipment, it is the most basic thing. If you need it, I can provide you, everyone can try it with himself. This part of the things, etc. I have time I have time to write a stuff.
Chapter 1 Basic Knowledge
This chapter mainly introduces some basic knowledge, such as history, excellent point, can not look, but suggestions or read, which is conducive to this language has an overall understanding. The other last section is still to look at the design process of Verilog HDL, although I may not write anything, but to form a concept, know how this thing is developed.
First section hardware description language
Hardware Description Language HDL (Hardware Description Language) is a language using a formal way to describe the language of digital circuits and systems. Designers of digital circuit systems use this language to describe their design ideas from the upper layer (from abstraction to specific), and use a series of hierarchical modules to express extremely complex digital systems. Then use the EDA tool to simulate the simulation verification, and then the module combination therein is converted into a gate-level circuit network via the automatic integrated tool. Next, a dedicated integrated circuit (ASIC) or field programmable gate array (FPGA) automatic layout wiring tool converts the menu into a specific circuit wiring structure. Hardware Description Language has been more than 20 years of history. The main language VHDL (Very High Speed Integerated Hardware Description Language) and Verilog Hardware Description Language adapted to historical development trends and requirements, and successively became the IEEE standard.
From me, the appearance of the language is to describe the design of the graphicization (component scraping), write the functions of the functions and the language we have to implement, and the work to convert to the actual circuit will be handed over to the EDA tool. Thereby simplifying our design, saving the development time. It can also be said that people who don't understand hardware don't have to understand too much about the circuit's things, you can start to do development, which may be more useful for researchers.
The history of Verilog HDL
Verilog HDL is a hardware description language for digital electronic system design. This language is the first 1983 Phil Moorby from GDA (GATEWAY Design Automation). Phil Moorby later became the first partner of Verilog-XL's main designer and Cadence Design System. In 1984-1985, Phil Moorby designed the first emulator called Verilog-XL; in 1986, he made a huge contribution to the development of Verilog HDL - proposed XL algorithm for fast-level simulation .
With the success of the Verilog-XL algorithm, Verilog HD language has developed rapidly. In 1989, Cadence acquired GDA, Verilog HDL language became the private property of Cadence. In 1990, Cadence decided to open the Verilog HDL language and set up OVI (Open Verilog International) organization and responsible for promoting the development of Verilog HDL language. Based on the superiority of Verilog HDL, IEEE has developed Verilog HDL IEEE standard in 1995, which released Verilog HDL1364-2001 standard in 2001. These two standards can be found on the network, and there are also Chinese version of the standard behind the Summer. Don't underestimate these two standards, it is still very useful for our programming, in some grammar and usage, comprehensive aspects, it is a quick-check manual, I often use this thing.
Comparison of Verilog HDL and VHDL
This thing seems to be quite important, because when you start, you should choose any language. To compare the advantages and disadvantages of the two languages, the case of use, etc., will be better learning. I will only verilog, so I don't dare to make the advantages and disadvantages between the two, I want to talk from another angle.
Both languages are hardware description languages for digital electronic system design, and are already the standard of IEEE. VHDL has become a standard in 1987, while Verilog is a standard in 1995. This is because VHDL is developed by the US military, and Verilog is a company's private property transformation. Why can Verilog be a IEEE standard? It must have its superiority, so Verilog has a stronger vitality. Both have their common feature:
1. Can formally abstract the behavior and structure of the circuit;
2. Support the layering and scope of the logical design;
3. Available in high-level language and simplify circuit behavior and structure; has circuit simulation and verification mechanism to ensure the correctness of the design;
4. Support circuit description consolidated by the high level to the low layer;
5. Hardware descriptions and implementation of the process;
6. Easy to manage document management;
7. Easy to understand and design reuse - this is very important!
But both are also characterized. Verilog HDL has been launched for 20 years, with a wide range of design groups, mature resources are also rich than VHDL (but as if I am looking for information, there are more information about VHDL, this and the present atmosphere). Verilog's greater advantage is that it is very easy to master, as long as there is a C language programming foundation, through a short time, after some actual operation, you can master this design technology within 2 to 3 months. The VHDL design is relatively difficult, this is because VHDL is not very intuitive, you need an ADA programming basis (I don't know what, dizzy), generally think that at least half a year of professional training can be mastered.
The current version of Verilog HDL and VHDL have different coverage ranges of behavioral abstract modeling. Verilog is generally considered to be slightly different than VHDL in system-level abstraction, while in terms of gate-class switching circuit description.
In the past 10 years, the EDA industry has been in the design of which hardware description language in digital logic, currently in the United States, high-level digital system design, and the ratio of Verilog and VHDL is 80% and 20%; Japan It's almost similar to Taiwan and the United States; it is better in Europe. Many integrated circuit design companies in China use Verilog, but VHDL also has a certain market.
Xia Teacher recommended to learn Verilog first, then learn vhdl. I think it is also, only a language is not enough, otherwise there will be problems on the communication, and the digital circuit is also a must-have to use the schematic method. Otherwise, you can't have a soft and hard pass, to achieve the level of big cow. .
The fourth section hardware description language design complex digital circuit
The previous digital logic circuit and the size of the system are relatively small and simple, and the input method for circuit schematic is basically enough. However, general engineers need handwiring, need to be familiar with the internal structure of the device and external leads, in order to achieve design requirements, this workload and design cycle is not what we can imagine. The time and cycle of design requirements are now very short, and this method is obviously not in line with the principle.
The comparison of the Verilog design method and the traditional circuit schematic input method: one is the design cycle shortage short, and the hardware description language and process are independent, this greatly reduces the workload. Some constraints related to hardware, some requirements for the chip can be handed over to the EDA tool, which greatly accelerates the design speed, reducing the workload of the engineer, thus improving the design of × × (I don't know how to describe).
The following three concepts: soft core, solid core and hard core.
Soft core refers to a Verilog HDL model that functionally verified, integrated, and rear digital architectural generals in more than 5,000 doors. Firm core refers to a circuit structure encoding file that is correct on a field programmable gate array (FPGA) device.
Hard core refers to a circuit structure layout of a circuit structure of more than 5,000 or more.
The soft core has the greatest flexibility, which can be combined with other designs as a combination with other design, and the solid core and hard core are relatively poor, so we need to focus on the design and promotion of soft cores. Reuse technology. In addition, devices composed of soft cores are called virtual instruments, and internationally a organization is called "Virtual Socket Interface Alliance to coordinate the work of the duplicate use of the virtual instrument.
Section 5 Verilog HDL design process
The current digital circuit system is particularly large, and it is necessary to design such a large system. If there is a little error in the middle, it will affect the correcting system. The current system design is generally divided by the total designer to divide the entire hardware design task into several parts, computing the corresponding model (behavior or structure), and then assigns each module to the following by simulation. engineer. The following engineers refine the work in the hand. This can separate a large system into many small systems separately designed by multi-person design, thereby increasing the design speed and shortening the development cycle. Moreover, some parts can utilize the use of IP cores (some mature business modules), more efficient development. Such a design concept is called top-down.
The top-down design is starting from the system level, dividing the system into several basic units, and then divides these basic cells into the next level of basic units, which can always be implemented in the EDA element library.
In fact, I understand that a number of projects have been refined, divided into ABCD ..., and each part continues to refine, such as A1, A2, A3, A1 below A1, A1, A1_2, two parts. A1¬_1 can be composed of three triggers and three and non-door so that it can be more convenient.
With regard to hierarchical management, the concept is not much here, summing up the process of using language, usually this:
1. Text Editing: You can use any text editor or edit the environment with a dedicated HDL. Usually the Verilog HDL file is saved as .v file.
2. Functional simulation: Turn the file to the HDL emulation software for functional simulation, check if the logical function is correct (also called before the simulation, skipping this step, only after the wiring is completed, it will be timed).
3. Logic synthesis: Source file transfer to logic integrated software, that is, integrated language into the simplest Boolean expression. Logic integrated software generates. EDA industry standard files for .edf (edif). (It is best to integrate with Max Plus II, because only the subset of VHDL / VERILOG HDL)
4. Layout wiring: Put the .edf file into the software provided by the PLD manufacturer, ie the logic of the design is placed into the CPLD / FPGA.
5. Timing simulation: need to utilize the precise parameters obtained in the layout wiring, use the simulation software to verify the timing of the circuit (also after the simulation). The stupid is over, a lot of things is on the book of the teacher, a little sweat -_- !!!
I hope that the things you write will be better, I found that what I wrote is really bitter, and I will not copy it ...
Chapter 2, Item Verilog HDL
This chapter I want to briefly introduce what Verilog HDL, with the actual example to illustrate the characteristics and structure of the general Verilog HDL program.
First section outline
I have to start talking about something bad ...
Simply talking about a Verilog HDL is a circuit module, such as a multi-channel selector. This structure from its program can be obvious (it seems that the program has not been seen?!). The main program of the C language is a master, and then there are many subunies, and the main function is generally included in a pair of braces.
Void main ()
{
// Program theme
}
The Verilog HDL program is included between keyword module and endmodule. Module means module, so I haven't false, but it is also convenient to remember these two keywords.
Before you officially explain the program, let's take a look at the circuit levels described, the book is "the Verilog model can be an abstraction of the different levels of the actual circuit", and it is simple to talk about the relationship between the specific circuit level.
Mainly divided into 5 categories:
System-Level
2. Algorithm-Level
3. RTL level (Register Transfer Level)
4. Gate-Level
5. Switch-Level
The first three are behavioral descriptions, which only RTL levels and logic circuits have clear correspondence. The fourth and logic circuits also have a clear link relationship. The fifth and specific physical circuits have a relationship. General Digital System Design Engineers must master four previous.
Why is this category? Because of the module written in different styles and structures, it is necessary to integrate into a practical circuit through the integrated tool, but these modules are not integrated into circuitry, and some only need to implement their logic functions, used in simulation, Verify the correctness of other modules, such as excitation signals, and the like.
This also refers to a comprehensive concept, and I understand that I understand that the module we write into actual circuit mesh is converted through the EDA tool. However, not every module, all statements can be synthesized, so pay special attention to and understand the comprehensive programming style while learning Verilog. This is not a clear one sentence, and it is only to understand in the process of learning. (About this online version of the Cambridge University Photocopy version of the "integrated Verilog syntax", interested friends can go to see.)
I was ready to write a complete tutorial, but the energy and time were limited, and the book of Xia teacher was good. The meaning I wrote the tutorial is not very big, so I want to learn the digital system design. Committed to FPGA / CPLD developed friends to buy this book, absolutely benefit for life.
My blog: http://blog.april9th.com/
