Now GPIO has two versions, 1.00A and 2.00A. Support for Channel is only in 2.00A. Only 1.00A does not have the concept of Channel, but in order to unify, just a GPIO of 1.00A has only one Channel.
V1.00A:
#define xgpio_data_offset 0x00000000 # Define XGPIO_TRI_OFFSET 0x00000004
#define xgpio_msetdataDirection (baseaddress, directionmask) / xgpio_mwritereg ((baseaddress), XGPIO_TRI_OFFSET, (DirectionMask)
#define xgpio_mwritered (BaseAddress, Regofset, Data) / (XIO_OUT32 (Regoffset), (Xuint32) (DATA))))))
#define xgpio_msetdataareg (baseaddress, data) / XGPIO_MWRITEREG ((BaseEaddress), XGPIO_DATA_OFFSET, (DATA))
#define xgpio_mreadreg (baseaddress, regofst) / (XIO_IN32 ((BaseAddress) (Regoffset))))
#define xgpio_mgetdataareg (baseaddress) / xgpio_mreadreg (baseaddress, XGPIO_DATA_OFFSET)
V2.00A:
#define XGPIO_DATA_OFFSET 0x0 / **
#define XGPIO_GIER_OFFSET 0x11C / ** #define xgpio_chan_offset 8 #define xgpio_ir_mask 0x3 / ** #define XGpio_mSetDataDirection (BaseAddress, Channel, DirectionMask) / XGpio_mWriteReg ((BaseAddress), / (((Channel) - 1) * XGPIO_CHAN_OFFSET) XGPIO_TRI_OFFSET, / (DirectionMask)) # define XGpio_mWriteReg (BaseAddress, RegOffset, Data) / XIo_Out32 ( (BaseadDress) (Regoffset), (Xuint32) (DATA)) #define XGPIO_MSETDATAREG (Baseaddress, Channel, DATA) / XGPIO_MWRITEREG (((Channel), / ((Channel) - 1) * XGPIO_CHAN_OFFSET) XGPIO_DATA_OFFSET, / (DATA)) #define xgpio_mreadreg (baseaddress, regofset) / XIO_IN32 ((BaseEaddress) (Regoffset)) #define XGPIO_MGETDATAREG (BaseAddress, Channel) / XGPIO_MREADREG ((BaseEaddress), / ((CHANNEL) - 1) * XGPIO_CHAN_OFFSET) XGPIO_DATA_OFFSET) In the later version, 8Bytes from BaseAddress belongs to CHANNEL1, then 8bytes belongs to Channel2. In the first 8bytes, the first 4 BYTES is a data register, and the 4bytes is the direction register (Xilinx uses 4bytes to do direction registers, this is extravagant I can't understand it), the post 8bytes is also all assigned. In addition, there is an address setting of the interrupt MASK register in the later version, and can be found in the header file XGPIO_L. The most important thing is that XGPIO_MSETDATAREG () and XGPIO_MWRITEREG () two functions (XGPIO_MREADREG () and XGPIO_MGETDATAREG () are the same.). XGPIO_MSETDATAREG () function name is already very clear, is used to set up the GPIO data register, write 32BITS data, V2.00A needs to be defined as the DataReg of CHANNEL1, or Channel's DataReg, and written The address has been basically determined because the offset of the data register is fixed relative to the GPIO device base. XGPIO_MWRITEREG () is a write register, any register, that is not necessarily the data register, its parameter regofset is the offset relative to the GPIO device base, if less than 8, written is the REG of CHANEL1, more than 8 less than 16 is the REG of Channel2, but if the regofset is not 4 times, the result writes from the register will become obscured (if 2, then set the first 2bytes and direction registers of the Channel1 data register). From the macro definition of XGPIO_MWRITEREG (), if you assign a relatively large number or negative to the REGOFSET, you will also set the register of other devices, and I don't know if the compile period will report an error or warning.
