PCI Peripheral Component Interconnect (PCI), like its name suggests how to connect to a standard for connecting the peripheral components in the system through a structured and controlled manner. The standard PCI Local Bus specification describes the method of electrical connection of system components and methods of their behavior. This chapter explores the Linux core how to initialize the system's PCI bus and equipment. Figure 6.1 is a logic diagram of a system of a PCI basis. The PCI bus and the PCI-PCI bridge (bridge) are adhesives associated with the system components. CUP and VIDEO devices are connected in the primary PCI bus, PCI bus 0. A special PCI device, the PCI-PCI bridge connects the main bus to the second PCI bus, the PCI bus 1. According to the term PCI specification, the PCI bus 1 describes the downstream of the PCI-PCI bridge and the PCI bus 0 is upstream of the bridge. Connecting to the second PCI bus is the system's SCSI and Ethernet devices. Physical bridge, secondary PCI bus and these two devices can be on the same PCI card. The PCI-ISA bridge in the system supports old, legacy ISA equipment, which shows a super I / O control chip, control keyboard, mouse, and floppy drive. 6.1 PCI Address Space The CPU and PCI devices require access to the memory shared. These memory allows the device driver to control these PCI devices and deliver information between them. The typical memory includes the control and status register of the device. These registers are used to control the device and read it. For example, the PCI SCSI device driver can read the status register of the SCSI device to determine if it can write a piece of information to the SCSI disk. Or it can write to the control register to turn it off to start running. The system memory used by the CPU can be used as this shared memory, but if so, each PCI device accesses the memory, the CPU has to stop, waiting for the PCI device to complete. Access to memory is usually limited, and only one system component allows access at the same time. This will make the system speed reduction. Allowing the system's external equipment to access the main memory in an uncontrolled manner is not a good idea. This will be very dangerous: a malicious device will make the system very unstable. External equipment is made by their own memory space. The CPU can access these spaces, but the device is strictly controlled for the access of the system memory, and must be passed through the DMA (Direct Memory Access Direct memory access) channel. ISA devices can access two address spaces: ISA I / O (input / output) and ISA memory. PCI is 3: PCI I / O, PCI Memory and PCI Configuration Spaces. The CPU can access all address space where the PCI I / O and PCI memory address space are used by the device driver and the PCI configuration space is used by the PCI initialization code in Linux and the heart. The Alpha AXP processor does not have a natural access mode for address spaces other than the system address space. It needs to use support chips to access other address spaces such as PCI configuration space. It uses an address space mapping scheme that is mapped to the PCI address space from a huge virtual address space. 6.2 PCI Configuration Headers Each PCI device in the system, including the PCI-PCI bridge, by a configuration data structure, located in the PCI configuration address space. The PCI configuration header allows system identification and control devices. This head is based on the exact location of the PCI configuration address space depends on the PCI topology used by the device.
For example, a PCI display card configuration header inserted in a PC motherboard is in a location, and if it is plugged into another PCI slot, its head will appear in another location in the PCI configuration memory. However, regardless of these PCI devices and bridges, the system can discover and use the status and configuration registers in their configuration headers to configure them. Typically, the system is designed such that the PCI configuration header of each PCI slot has an offset associated with a slot on the board. Therefore, for example, the PCI configuration of the first slot on the board may be located at offset 0 and the second slot is offset 256 (all heads are the same length, 256 bytes), so that this is pushed. Defining the system-related hardware mechanism allows the PCI configuration code to try all possible PCI configuration heads on a given PCI bus, trying to read a domain in the head (usually the vendor identification domain) get some errors, Those devices are exist and those devices do not exist. The PCI Local Bus specification describes a possible error message: Trying to read the Verdor Identification and Device Indentification domain of an empty PCI slot and Device Indentification Domain Returns 0xFffffFFFF. Figure 6.2 shows the layout of 256 bytes of PCI configuration headers. It includes the following domain: see the unique number of include / Linux / pci.hvendor Identification, describing the inventors of this PCI device. Digital's PCI vendor Identification is 0x1011 and Intel is 0x8086. Device Identification Describes the unique number of the device itself. For example, Digital 21141 Fast Ethernet device's device identifier is 0x0009. STATUS This domain gives the state of the device, and its bitmap is specified by the PCI Local Bus specification. The Command system controls this device by writing this domain. For example: Allows the device to access PCI I / O memory. Class Code identifies the type of device. For each device, there is a standard classification: display, SCSI, and more. Type encoding for SCSI is 0x0100. Base Address Registers These registers are used to determine and allocate the type, size, and location of PCI I / O and PCI memory that can be used. 4 of the physical pins of the Interrupt PIN PCI card is used to transfer interrupts to the PCI bus. They are marked as A, B, C, and D in the standard. The Interrupt PIN domain describes this PCI device to use that pin. It is usually determined at this time for a device. That is to say, when the system starts, this device uses the same interrupt pin. This information allows interrupt processing subsystem to manage interrupts of these devices. The Interrupt Line field in the Interrupt Line PCI configuration head is used to transfer interrupt control between the PCI initialization code, the device driver, and Linux interrupt processing subsystem. The numbers written here are meaningless for the device driver, but it allows the interrupt handler to correctly send an interrupt from the PCI device to the correct device driver in the Linux operating system. How Linux handles interrupts to see Chapter 7. 6.3 PCI I / O and PCI Memory Address (PCI I / O and PCI Memory Address) These two address spaces are used for their device driver communication that is running on the device and the CPU. For example: Decchip 21141 Fast Ethernet device maps its internal registers to PCI I / O space. It then controls the device by reading and writing these registers. Display drivers typically use a large number of PCI memory space to place display information.
These spaces are unable to access these spaces until the PCI system is established and using the Command field in the PCI configuration header. It should be noted that only the PCI configuration code reads and writes the PCI configuration address, the Linux device driver is just read and write the PCI I / O and PCI memory addresses. 6.4 PCI-ISA Bridges (PCI-ISA Bridge) This bridge converts access to PCI I / O and PCI memory address to ISA I / O and ISA memory access to support ISA devices. Most systems currently include several ISA bus slots and several PCI bus slots. This backward compatibility requires continuous reduction, and there will be only PCI systems in the future. At the early Intel 8080 foundation PC age, ISA address space (I / O and memory) of ISA devices in the system is fixed. Even the ISA I / O address of the ISA software drive of a computer system of S5000 Alpha Axp foundation will be the same as the first IBM PC. The PCI specification retains the lower area in the address space of PCI I / O and PCI memory to the ISA peripherals in the system and uses a PCI-ISA bridge to convert all PCI memory access to these regions to ISA access. 6.5 PCI-PCI Bridges (PCI-PCI Bridge) PCI-PCI bridge is a special PCI device, and the PCI bus in the system is sticky. There is only one PCI bus in the simple system, and the number of PCI devices that a single PCI bus can support has electrical restrictions. Add more PCI bus using the PCI-PCI bridge allows the system to support more PCI devices. This is especially important for high performance servers. Of course, Linux fully supports the use of the PCI-PCI bridge. 6.5.1 PCI-PCI Bridges: PCI I / O and PCI Memory Windows PCI-PCI Bridge onlys a subset of PCI I / O and PCI memory reading and writing. For example, in Figure 6.1, the PCI-PCI bridge only passes the read-write address from the PCI bus 0 to the bus 1 when the read and write addresses belong to SCSI or Ethernet devices, and the rest are ignored. This filter blocks unnecessary address information traversal systems. To achieve this, the PCI-PCI bridge must be programmed to set the foundation and restrictions of the PCI I / O and PCI memory address space access from the primary bus to the secondary bus. Once the PCI-PCI bridge in the system is set, as long as the Linux device driver is only passed through these windows, the PCI-PCI bridge is invisible. This is an important feature that makes the LINUX's PCI device driver's authors. But it also allows the PCI-PCI bridge under Linux to a certain extent, we will see it. We will see it soon. 6.5.2 PCI-PCI Bridges: PCI Configuration CYCLES AND PCI BUS NUMBERING (PCI-PCI Bridge: PCI Configuration Cycle and PCI Bus Number) Since the CPU's PCI initialization code can locate equipment that is not in the primary PCI bus, there must be a mechanism to make The bridge can decide whether to transfer the configuration cycle from its primary interface to the secondary interface. A cycle is the address it displayed on the PCI bus. The PCI specification defines two PCI address configuration formats: type 0 and type 1, shown in Figures 6.3 and 6.4, respectively. The PCI configuration of type 0 is not included in the PCI server, which is used for PCI address configuration.
Configuring the bit 32: 11 of CYCLE is seen as a device selection domain. A method of designing a system is to allow each bit to select a different device. In this case, 11 may select the PCI device of the slot 0, and the bit 12 selects the PCI device of the slot 1, and so on. Another method is to write directly to the slot number of the device in place 31: 11. One system uses which mechanism depends on the system's PCI memory controller. Type 1 PCI configuration CYCLE includes a PCI bus number that is ignored by all PCI devices other than the PCI-PCI bridge. All PCI-PCI bridges that have seen the type 1 PCI-PCI bridge can transmit this information to their downstream. Whether a PCI-PCI bridge ignores the PCI configuration loop or delivers it downstream, depending on how this bridge is configured. Each PCI-PCI bridge has a main bus interface number and a secondary bus interface number. The main bus interface is closest to the CPU, the secondary bus interface is farthest from the CPU. Each PCI-PCI bridge has an accessory bus number, which is the maximum number of PCI buss that can bridge over the second bus interface. Alternatively, the attached bus number is the largest PCI bus number downstream of the PCI-PCI bridge. When the PCI-PCI bridge sees a type 1 PCI configuration cycle, it does what is the following: If the specified bus number is not overlining it, it is ignored between the second bus number and the buse number of the bridge. If the specified bus number and the secondary bus number of the bridge meet the configuration command to convert it into type 0, if the specified bus number is larger than the secondary bus number, it is not changed to the secondary bus interface without changing the secondary bus number. on. So, if we want to address the device 1 on the topology of Figure 6.9, we must generate a type 1 configuration command from the CPU. The bridge 1 does not change to the bus 1, the bridge 2 ignores it but the bridge 3 converts it into a type 0 configuration command, and send it to the bus 3, allowing the device 1 to respond. Each independent operating system is responsible for assigning a bus number in the PCI configuration phase, but no matter which coding scheme is used, the following statements must be correct for all PCI-PCI bridges in the system: all behind a PCI-PCI bridge The PCI bus coding must be between the secondary bus number and the affiliate bus number (included) If this rule is contrary to this rule, the PCI-PCI bridge will not be able to correctly transmit and convert the PCI configuration of the transition type 1, and the system cannot succeed. Find and initialize the PCI device in the system. In order to complete the encoding scheme, Linux configures these special devices in a specific order. See Section 6.6.2 For the description of the Linux PCI bridge and bus coding scheme, and an example of work. 6.6 Linux PCI Initialization (Linux PCI Initialization Procedure) Linux PCI initialization code is divided into three logical part: PCI Device Driver Drivers Since the PDCI from bus 0, all PCI systems are locked in the positioning system and bridges. It establishes a list of a list of data structures to describe the topology of the system. In addition, it also encodes all the bridges in the system. See drivers / pci / pci.c and include / linux / pci.h PCI BIOS This software layer provides the services described in the PCI BIOS ROM specification. Even if Alpha Ax does not have a BIOS service, there is an equivalent code for the same function in Linux core. See Arch / * / Kernel / Bios32.cpci Fixup system-related organizational code, finishing, and system-related cases where PCI initialization last memory is loose.
See Arch / * / kernel / Bios32.c6.6.1 Linux Kernel PCI Data Structures (Linux core PCI data structure) When the Linux core initializes the PCI system, it establishes the data structure of the real PCI topology. Figure 6.5 shows the relationship between the data structure, which is used to describe the PCI system shown in Figure 6.1. Each PCI device (including PCI-PCI bridge) is described in a PCI_DEV data structure. Each PCI bus is described with a data structure of a PCI_Bus. The result is a tree-like structure of a PCI bus, and some sub-PCI devices are adhered to each bus. Because a PCI bus can only reach the PCI-PCI bridge (except for the main PCI bus, bus 0), each PCI_BUS includes a pointer to the PCI device it passes (this PCI-PCI bridge). This PCI device is a sub-device for the parent bus of this PCI bus. Figure 6.5 is not displayed in the pointer to all PCI devices in the system: PCI_Devices. The data structure of all PCI_DEVs in the system is located in this queue. Linux core uses this queue to quickly find all PCI devices in the system. 6.6.2 The PCI Device Driver (PCI Device Driver) The PCI device driver is not a real device driver, just a function of operating the system call when the system is initialized. The PCI initialization code must scan all PCI bus in the system to find all PCI devices in the system (including PCI-PCI bridge devices). It uses the PCI BIOS code to see if each possible slot on its currently scanned PCI bus is occupied. If this PCI slot is occupied, it creates a PCI_DEV data structure describing the device and links it to the list of known PCI devices (pointing by PCI_Dereates). See drivers / pci / pci.c scan_bus () PCI initialization code starts scanning from the PCI bus 0. It tries to read the Vendor Identification and Device Identification domain for each possible PCI device in each possible PCI slot. When it finds the slot of the occupied, it creates a PCI_DEV data structure to describe it. All PCI_DEV data structures established by the PCI initialization code (including all PCI-PCI bridges) are connected to a link table: PCI_Devices. If the found device is a PCI-PCI bridge, a PCI_Bus data structure is created and is linked to the tree whose PCI_ROOT is pointed to by the PCI_Bus and PCI_DEV data structures. The initial code of the PCI can determine if the PCI device PCI-PCI bridge is because its classification is 0x060400. The Linux core is then configured to configure the PCI bus (downstream) of the other end of the PCI-PCI bridge that it just found. If you find more PCI-PCI bridges, they are all configured. This process becomes a depthwize algorithm: the system is unfolded before the width search. Look at Figure 6.1, Linux will first configure the PCI bus 1 and its Ethernet and SCSI devices, and then configure the display device on the PCI bus 0. When LINUX looks for the PCI bus downstream, it must be configured to configure the secondary bus of the intervention PCI-PCI bridge and an affiliate bus number.
These are described in Section 6.6.2: Configuring PCI-PCI Bridges - Assigning PCI Bus Numbers (Configuring PCI-PCI Bridge - Assigning PCI Bus Number) For PCI I / O, PCI Memory, or PCI Configuration Address through them The space read and write, the PCI-PCI bridge must be until the following: Primary Bus Number Just in the PCI-PCI Bridge bus number Secondary Bus Number just in the PCI-PCI bridge bus number Subordinate Bus Number from this bridge downward The highest bus number in all buses. PCI I / O and PCI Memory Windows BASE and SIZE of the PCI I / O address space of this PCI-PCI bridge and the window of the PCI memory space. The problem is that when you want to configure any specified PCI-PCI bridge, you don't know the number of attached bus of this bridge. You don't know if there is another PCI-PCI bridge downstream. Even if you know, you don't know what number they will be assigned. The answer is to use a depth revitalization algorithm. They allocate numbers when they find any PCI-PCI bridges on each bus. For each PCI-PCI bridge found, the secondary bus is assigned, and it assigns the temporary subsidiatric bus number 0xff and scans all of its downstream PCI-PCI bridges and assigns numbers. This looks quite complicated, but the actual example below can make this process clearer. PCI-PCI Bridge Numbering: Step 1 Referring to the topology in Figure 6.6, the first bridge found by the scan is bridge 1 (bridge1). The PCI bus number downstream of the bridge 1 is 1, and the bridge 1 assigns a secondary bus number 1 and a temporary affiliated bus number 0xFF. This means that the PCI configuration address of the type 1 used to specify the PCI bus 1 or higher will pass through the bridge 1 to the PCI bus 1. If their bus number is 1, it is converted into a configuration cycle of type 0, otherwise it is unchanged for other bus numbers. This is also the Linux PCI initialization code needs to be done, so that the PCI bus 1 can be accessed and scanned. PCI-PCI Bridge Numbering: STEP 2 Linux Use a depth algorithm, so initialization code starts scanning the PCI bus 1. This is where it finds a PCI-PCI bridge 2, there is no other PCI-PCI bridge outside of the bridge 2, so its affiliate bus number is 2, and the interface is the same. Figure 6.7 shows how the bus and the PCI-PCI bridge are encoded. PCI-PCI Bridge Numbering: STEP 3 PCI initialization code comes back to scan the PCI bus 1, find another PCI-PCI bridge 3. Its main bus interface assigns a value of 1 and its secondary bus interface is 3, and its affiliate bus number is 0xFF. Figure 6.8 shows how the system is configured. The PCI configuration of type 1 with bus number 1, 2 or 3 can now be transmitted correctly to the appropriate PCI bus. 6.6.3 PCI BIOS Functions The PCI BIOS function is a series of standard routines for a general cross-platform. For example, they are the same for Intel and Alpha AxP systems. They allow CPUs to control access to all PCI address spaces. Only Linux core and device drivers need to use them.
See Arch / * / kernel / bios32.c6.6.4 PCI Fixup Alpha AxP system PCI finishing code than Intel (basically do not do anything) Do more work. For the Intel system, the system BIOS that is running is fully configured with the PCI system. Linux does not need to do more things, just mapping the configuration of the PCI. For non-Intel systems, you need more configurations: See Arch / Kernel / Bios32.c Assigning each PCI I / O and PCI memory space for each device for each PCI-PCI bridge that must be configured to configure PCI I / O and The PCI Memory Address window generates an Interrupt Line value for the device, which describes how these code works below. Finding Out How Much PCI I / O and PCI Memory Space A Device Needs (finding a device requires how much PCI I / O and PCI memory space) Query each PCI device found, find out how much PCI I / O and memory it takes Address space. To this end, all Base Address Register is written to 1 and then read it. The device returns 1 if the address bits do not care, effectively specify the required address space. With two basic base addresses registers, the first indicator register and which address space must be in the PCI I / O and PCI memory space. This is represented by 0 bits of registers. Figure 6.10 shows two forms of the basic address registers of PCI memory and PCI I / O. In order to find out how much address space required for each given underlying address register, you need to write and read all registers. The device will set the uncomfortable address bit to 0, which effectively indicates the required address space. This design suggests that all address spaces used are 2 indices, essentially aligned. For example, when you initialize Decchip 21142 PCI fast Ethernet device, it tells you that it requires an address of 0x100 bytes in PCII / O or PCI memory space. The initialization code is allocated with space. After it allocates space, the control and status register of 21142 can be seen in these addresses. Allocating PCI I / O and PCI Memory To PCI-PCI Bridges and Devices (Assign PCI-PCI Bridges and Devices) Like all memory, PCI I / O and PCI memory space are limited. Some of them are quite shortage. For non-Intel system PCI finishing code (and the BIOS code of the Intel system) must effectively assign the amount of memory it needs to each device. The allocation of PCI I / O and PCI memory assigned to one device must be naturally aligned. For example, if a device requests a PCI I / O address 0xB0, the assigned address must be a multiple of 0xB0. In addition, the basis of the PCI I / O and PCI memory addresses allocated to any bridge must be aligned separately from 4k and 1M boundaries. The downstream device given the address space must be located in the middle of all of its upstream PCI-PCI bridges. Therefore, it is difficult to effectively allocate address space. The algorithm used by Linux depends on each device described in the bus / device tree established by the PCI device driver, which assigns an address space in order of PCI I / O memory. It is also using the recursive algorithm, traversing the PCI_bus and PCI_DEV data structures established by the PCI initialization code.
