Typedef unsigned char xuint8; / ** Typedef char Xint8; / ** Typedef unsigned short xuint16; / ** Typedef short xint16; / ** TYPEDEF UNSIGNED Long Xuint32; / ** Typedef long xint32; / ** Typedef float xfloat32; / ** <32-bit floating point * / Typedef double xfloat64; / ** <64-bit double precision floating point * / TYPEDEF UNSIGNED Long Xboolean; / ** #define XIo_In8 (InputPtr) (* (volatile Xuint8 *) (InputPtr)) # define XIo_Out8 (OutputPtr, Value) {(* (volatile Xuint8 *) (OutputPtr) = Value);} #define XGpio_mWriteReg (BaseAddress, RegOffset, Data ) XIo_Out32 ((BaseAddress) (RegOffset), (Xuint32) (Data)) # define XGpio_mSetDataReg (BaseAddress, Channel, Data) / XGpio_mWriteReg ((BaseAddress), / (((Channel) - 1) * XGPIO_CHAN_OFFSET) XGPIO_DATA_OFFSET, / (Data)) # define XGpio_mReadReg (BaseAddress, RegOffset) XIo_In32 ((BaseAddress) (RegOffset)) # define XGpio_mGetDataReg (BaseAddress, Channel) / XGpio_mReadReg ((BaseAddress), / (((Channel) - 1) * XGPIO_CHAN_OFFSET) XGPIO_DATA_OFFSET) #define xtrue 1 # define Xfalse 0 #ifndef null # Define Null 0 # Endif # Define Xnull Null #define xcomponent_is_ready 0x11111111 / * Component Has Been Initialized * / # define XComponent_is_Started 0x22222222 / * Component Has Been Started * / #define xtest_parassed 0 # define Xtest_failed 1 #define XASSERT_NONE 0 # Define XASSERT_OCCURRED 1 extern unsigned int XAssertStatus; extern void XAssert (char *, int); typedef struct {Xuint32 Upper; Xuint32 Lower;} Xuint64; typedef struct {Xuint16 DeviceId; / * Unique ID of device * / Xuint32 BaseAddress; / * Device base address * / Xboolean InterruptPresent; / * Are interrupts supported in h / w * / Xboolean IsDual; / * Are 2 channels supported in h / w * /} XGpio_Config; typedef struct {Xuint32 BaseAddress; / * Device base address * / Xuint32 IsReady; / * Device is initialized and ready * / XGpio_Config * ConfigPtr; / * Pointer to the configuration * /} XGpio; typedef struct {Xuint32 TransmitInterrupts; / ** . / ** * This typedef contains configuration information for the device * / typedef struct {Xuint16 DeviceId; / ** XuartLite_Buffer SendBuffer; XuartLite_Buffer ReceiveBuffer; XUartLite_Handler RecvHandler; void * RecvCallBackRef; / * Callback reference for recv handler * / XUartLite_Handler SendHandler; void * SendCallBackRef; / * Callback reference for send handler * /} XUartLite; #define XST_SUCCESS 0L # define XST_FAILURE 1L # define XST_DEVICE_NOT_FOUND 2L # define XST_DEVICE_BLOCK_NOT_FOUND 3L # define XST_INVALID_VERSION 4L # define XST_DEVICE_IS_STARTED 5L # define XST_DEVICE_IS_STOPPED 6L # define XST_FIFO_ERROR 7L / * an error occurred during an operation with a FIFO such as an underrun or overrun, THIS ERROR Requires The Device To Be Reset * / # Define XSt_Reset_ERROR 8L / * An Error Occurred Which Requires The Device To Be Reset * / # Define XST_DMA_ERROR 9L / * A DMA Error Occurred, this error typically requires the device using the DMA to be reset * / # define XST_NOT_POLLED 10L / * the device is not configured for polled mode operation * / # define XST_FIFO_NO_ROOM 11L / * a FIFO did not have room to put the specified data into * / # define XST_BUFFER_TOO_SMALL 12L / * the buffer is not large enough to hold the expected data * / # define XST_NO_DATA 13L / * there was no data available * / # define XST_REGISTER_ERROR 14L / * a register did not contain the expected value * / # Define XST_INVALID_PARAM 15L / * An Invalid Parameter Was Passed INTO THE FUNCTION * / # Define XST_NOT_SGDMA 16L / * the device is not configured for scatter-gather DMA operation * / # define XST_LOOPBACK_ERROR 17L / * a loopback test failed * / # define XST_NO_CALLBACK 18L / * a callback has not yet been * registered * / # define XST_NO_FEATURE 19L / * device is not configured with * the requested feature * / # define XST_NOT_INTERRUPT 20L / * device is not configured for * interrupt mode operation * / # define XST_DEVICE_BUSY 21L / * device is busy * / # define XST_ERROR_COUNT_MAX 22L / * t he error counters of a device * have maxed out * / # define XST_IS_STARTED 23L / * used when part of device is * already started ie * sub channel * / # define XST_IS_STOPPED 24L / * used when part of device is * already stopped ie * Sub channel * // **************** UTILITY Component Statuses 401 - 500 ******************* / #define XST_MEMTEST_FAILED 401L / * MEMORY TEST FAILED * / / **************** Common Components Statuses 501 - 1000 ******************** / / ******************** Packet FIFO STATUS 501 - 510 ****************************** ** / #define XST_PFIFO_LACK_OF_DATA 501L / * not enough data in FIFO * / # define XST_PFIFO_NO_ROOM 502L / * not enough room in FIFO * / # define XST_PFIFO_BAD_REG_VALUE 503L / * self test, a register value was invalid after reset * / / ************************* DMA STATUS 511 - 530 **************************** ********* / #define XST_DMA_TRANSFER_ERROR 511L / * Self Test, DMA Transfer Failed * / # define XST_DMA_RESET_REGISTER_ERROR 512L / * SELF TEST, a register value was invalid after reset * / # define XST_DMA_SG_LIST_EMPTY 513L / * scatter gather list contains no buffer descriptors ready to be processed * / # define XST_DMA_SG_IS_STARTED 514L / * scatter gather not stopped * / # define XST_DMA_SG_IS_STOPPED 515L / * scatter gather not running * / # define XST_DMA_SG_LIST_FULL 517L / * all the buffer desciptors of the scatter gather list are being used * / # define XST_DMA_SG_BD_LOCKED 518L / * the scatter gather buffer descriptor which is to be copied over in the scatter list is locked * / # define XST_DMA_SG_NOTHING_TO_COMMIT 51 9L / * no buffer descriptors have been put into the scatter gather list to be commited * / # define XST_DMA_SG_COUNT_EXCEEDED 521L / * the packet count threshold specified was larger than the total # of buffer descriptors in the scatter gather list * / # define XST_DMA_SG_LIST_EXISTS 522L / * The scatter Gather List Has Already Been Created * / # define XST_DMA_SG_NO_LIST 523L / * No Scatter Gather List HAS been created * / # define XST_DMA_SG_BD_NOT_COMMITTED 524L / * the buffer descriptor which was being started was not committed to the list * / # define XST_DMA_SG_NO_DATA 525L / * the buffer descriptor to start has already been used by the hardware so it can not be reused * // ********************************************************************************************************************************************************************************************************************************************************* *********** / #define XST_IPIF_REG_WIDTH_ERROR 531L / * an invalid register width was passed into the function * / # define XST_IPIF_RESET_REGISTER_ERROR 532L / * the value of a register at reset was not valid * / # define XST_IPIF_DEVICE_STATUS_ERROR 533L / * a write to the device interrupt status register did not read back correctly * / # define XST_IPIF_DEVICE_ACK_ERROR 534L / * the device interrupt status register did not reset when acked * / # define XST_IPIF_DEVICE_ENABLE_ERROR 535L / * the device interrupt enable register was not updated when other registers changed * / # define XST_IPIF_IP_STATUS_ERROR 536L / * a WR ite to the IP interrupt status register did not read back correctly * / # define XST_IPIF_IP_ACK_ERROR 537L / * the IP interrupt status register did not reset when acked * / # define XST_IPIF_IP_ENABLE_ERROR 538L / * IP interrupt enable register was not updated correctly when other registers changed * / # define XST_IPIF_DEVICE_PENDING_ERROR 539L / * The Device Interrupt Pending Register Did Not Indicate The EX PECTED VALUE * / # define xst_ipif_device_id_errupt ID register Did NOT INDICATE The expected value * // *************************** DEVICE SPECIFIC STATUS 1001 - 4095 ** ****************** / / ******************** Ethernet Statuses 1001 - 1050 **************************************** ** / #define XST_EMAC_MEMORY_SIZE_ERROR 1001L / * Memory space is not big enough * to hold the minimum number of * buffers or descriptors * / # define XST_EMAC_MEMORY_ALLOC_ERROR 1002L / * Memory allocation failed * / # define XST_EMAC_MII_READ_ERROR 1003L / * MII read error * / # define XST_EMAC_MII_BUSY 1004L / * An MII operation is in progress * / # define XST_EMAC_OUT_OF_BUFFERS 1005L / * Adapter is out of buffers * / # define XST_EMAC_PARSE_ERROR 1006L / * Invalid adapter init string * / # define XST_EMAC_COLLISION_ERROR 1007L / * Excess deferral or late * collision on polled Send * / / *********************** UART STATUSES 1051 - 1075 ******************************* ****** / # define xst_uart #define XST_UART_INIT_ERROR 1051L # define XST_UART_START_ERROR 1052L # define XST_UART_CONFIG_ERROR 1053L # define XST_UART_TEST_FAIL 1054L # define XST_UART_BAUD_ERROR 1055L # define XST_UART_BAUD_RANGE 1056L / *********************** IIC STATUSES 1076 - 1100 ******************** ******* / #define XST_IIC_SELFTEST_FAILED 1076 / * self test failed * / # define XST_IIC_BUS_BUSY 1077 / * bus found busy * / # define XST_IIC_GENERAL_CALL_ADDRESS 1078 / * mastersend attempted with * / / * general call address * / # define XST_IIC_STAND_REG_RESET_ERROR 1079 / * A non parameterizable reg * / / * value after reset not valid * / # define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 / * Tx fifo included in design * / / * value after reset not valid * / # define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 / * Rx fifo included in design * / / * value after Reset not valid * / # define XST_IIC_TBA_REG_RESET_ERROR 1082 / * 10 Bit Addr Incl in Design * / / * Value After Reset Not Valid * / # define XST_IIC_CR_READBACK_ERROR 1083 / * Read of THE CONT rol register * / / * did not return value written * / # define XST_IIC_DTR_READBACK_ERROR 1084 / * Read of the data Tx reg * / / * did not return value written * / # define XST_IIC_DRR_READBACK_ERROR 1085 / * Read of the data Receive reg * / / * did not return value written * / # define XST_IIC_ADR_READBACK_ERROR 1086 / * Read of the data Tx reg * / / * did not return value written * / # define XST_IIC_TBA_READBACK_ERROR 1087 / * Read of the 10 bit addr reg * / / * DIDN ' THE Device Isn't a slave * // **************************************************** ATMAC STATUSES 1101 - 1125 *********************************** / #define XST_ATMC_ERROR_COUNT_MAX 1101L / * The Error Counters in The ATM Controller Hit The max value Which request the statistics to be pas cleared * / / ********************** FLASH Statuses 1126 - 1150 ******************************* ***** / #define XST_FLASH_BUSY 1126L / * Flash is erasing or programming * / # define XST_FLASH_READY 1127L / * Flash is ready for commands * / # define XST_FLASH_ERROR 1128L / * Flash had detected an internal error. Use XFlash_DeviceControl to retrieve device specific codes * / # define XST_FLASH_ERASE_SUSPENDED 1129L / * Flash is in suspended erase state * / # define XST_FLASH_WRITE_SUSPENDED 1130L / * Flash is in suspended write state * / # define XST_FLASH_PART_NOT_SUPPORTED 1131L / * Flash type not supported by driver * / # define XST_FLASH_NOT_SUPPORTED 1132L / * Operation not supported * / # define xst_flash_too_many_regions 1133l / * Too Many Erase Regions * / # define XST_FLASH_TIMEOUT_ERROR 1134L / * Programming Or Erase Operation Aborted Due To a Timeout * / # define XST_ FLASH_ADDRESS_ERROR 1135L / * Accessed flash outside its addressible range * / # define XST_FLASH_ALIGNMENT_ERROR 1136L / * Write alignment error * / # define XST_FLASH_BLOCKING_CALL_ERROR 1137L / * Could not return immediately from write / erase function with XFL_NON_BLOCKING_WRITE / ERASE option cleared * / # define XST_FLASH_CFI_QUERY_ERROR 1138L / * Failed to Query the Device * / / *********************** SPI STATUSES 1151 - 1175 ******************************** ******* / # define XST_SPI_MODE_FAULT 1151 / * master was selected as slave * / # define XST_SPI_TRANSFER_DONE 1152 / * data transfer is complete * / # define XST_SPI_TRANSMIT_UNDERRUN 1153 / * slave underruns transmit register * / # define XST_SPI_RECEIVE_OVERRUN 1154 / * device overruns receive register * / # define XST_SPI_NO_SLAVE 1155 / * no slave has been selected yet * / # define XST_SPI_TOO_MANY_SLAVES 1156 / * more than one slave is being * selected * / # define XST_SPI_NOT_MASTER 1157 / * operation is valid only as master * / # define 1158 / * Device is configured as slave-only * / # define xst_spi_slave_mode_fault 1159 / * slave was selected while disabled * // ********************** ** OPB Arbiter Statuses 1176 - 1200 ******************** / #define XST_OPBARB_INVALID_PRIORITY 1176 / * the priority registers have either * one master assigned to two or more * priorities, or one master not * assigned to any priority * / # define XST_OPBARB_NOT_SUSPENDED 1177 / * an attempt was made to modify the * priority levels without first * suspending the use of priority * levels * / # define XST_OPBARB_PARK_NOT_ENABLED 1178 / * bus parking by id was enabled but * bus parking was not enabled * / # define XST_OPBARB_NOT_FIXED_PRIORITY 1179 / * the arbiter must be in fixed * priority mode to Allow the * priorities to be change * // ********************** INTC STATUSES 1201 - 1225 *********** *************** / #define XST_INTC_FAIL_SELFTEST 1201 / * SELF TEST FAILED * / / Define XST_INTC_CONNECT_ERROR 1202 / * Interrupt Already in use * / / ********************* TMRCTR STATUSES 1226 - 1250 ************************************ **** / #define XST_TMRCTR_TIMER_FAILED 1226 / * SELF TEST FAILED * / / ********************************************************* ***** / #define XST_WDTTB_TIMER_FAILED 1251L / ********************* PLBARB STATUSES 1276 - 1300 ************************** **** / #DEFINE XST_PLBARB_FAIL_SELFTEST 1276L / *********************** **************************************** ******* / #define XST_PLB2OPB_FAIL_SELFTEST 1301L / ********************* OPB2PLB Statuses 1326 - 1350 *********************** *** / #define XST_OPB2PLB_FAIL_SELFTEST 1326L / ********************** SYSACE STATUSES 1351 - 1360 ****************************** **** / #define xst_sysace_no_lock 1351L / * No MPU LOCK HAS BEEN Grand * / / ********************** PCI bridge statuses 1361 - 1375 ********************** * / #define XST_PCI_INVALID_ADDRESS 1361L / ********************************************************** ************ / / ** * The status typef. * / Typef xuint32 xstatus; / ************************************************ **************************************** * * SYSTEM Level Defines. These constants are for devices that do not require * a device driver. Examples of these types of devices include volatile RAM * devices. * / # define XPAR_ZBT_NUM_INSTANCES 1 # define XPAR_ZBT_0_BASE 0x00000000 # define XPAR_ZBT_0_SIZE 0x00100000 #define xpar_sram_num_instances 1 # define xpar_sram_0_base 0x00100000 # Define XPar_sram_0_size 0x00200000 #define xpar_ddr_num_instances 1 # define xpar_ddr_0_base 0xf0000000 # define xpar_ddr_0_size 0x01000000 #define xpar_core_clock_freq_hz 12500000 #define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ XPAR_CORE_CLOCK_FREQ_HZ / ************************************************** *************************** * * Interrupt Controller (INTC) defines. * DeviceID Starts AT 0 * / # define xpar_xintc_num_instances 2 / * Number of instances * / # define XPAR_INTC_MAX_NUM_INTR_INPUTS 31 / * max # inputs of all * / # define XPAR_INTC_SINGLE_BASEADDR 0x70800000 / * low level driver base * / # define XPAR_INTC_SINGLE_DEVICE_ID 0 / * single instance ID * / # define XPAR_INTC_SINGLE_ACK_BEFORE 0xFFFF00FF / * low level driver * / # define XPAR_INTC_0_DEVICE_ID 1 / * Device ID for instance * / # define XPAR_INTC_0_ACK_BEFORE 0xFFFF00FF / * Ack timing, before / after * / # define XPAR_INTC_0_BASEADDR 0x70800000 / * Register base address * / #define XPAR_INTC_0_UARTLITE_0_VEC_ID 4 / * Interrupt source for vector * / # define XPAR_INTC_0_WDTTB_0_VEC_ID 5 / * Interrupt source for vector * / # define XPAR_INTC_0_WD_0_VEC_ID 6 / * Interrupt source for vector * / # define XPAR_INTC_0_TMRCTR_0_VEC_ID 7 / * Interrupt source for vector * / # define XPAR_INTC_0_SPI_0_VEC_ID 11 / * Interrupt source for vector * / # define XPAR_INTC_0_IIC_0_VEC_ID 12 / * Interrupt source for vector * / # define XPAR_INTC_0_UARTNS550_0_VEC_ID 13 / * Interrupt source for vector * / # define XPAR_INTC_0_UARTNS550_1_VEC_ID 14 / * Interrupt source for vector * / # define XPAR_INTC_0_EMAC_0_VEC_ID 15 / * Interrupt Source for Vector * / #define XPAR_INTC_1_DEVICE_ID 2 / * Device ID for instance * / # define XPAR_INTC_1_ACK_BEFORE 0xFFFF00FF / * Ack timing, before / after * / # define XPAR_INTC_1_BASEADDR 0x70800020 / * Register base address * / #define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0 / * Interrupt source for vector * / # define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1 / * Interrupt source for vector * // ************************* *********************************************************** ** * * Ethernet 10/100 Mac defines. * DeviceID Starts AT 10 * / # define xpar_xemac_num_instances 1 / * Number of Instances * / #define XPAR_EMAC_0_DEVICE_ID 10 / * Device ID for instance * / # define XPAR_EMAC_0_BASEADDR 0x60000000 / * Device base address * / # define XPAR_EMAC_0_DMA_PRESENT XFALSE / * Does device have DMA? * / # define XPAR_EMAC_0_ERR_COUNT_EXIST XTRUE / * Does device have counters? * / # DEFINE XPAR_EMAC_0_MII_EXIST XTRUE / * DOES Device Support MII? * / / ************************************************** ************************************* * * NS16550 UART Defines. * DeviceID Starts AT 20 * / # define xpar_xuartns550_num_instances 1 / * Number of Instances * / #define XPAR_UARTNS550_0_DEVICE_ID 20 / * Device ID for instance * / # define XPAR_UARTNS550_0_BASEADDR 0xA0010000 / * IPIF base address * / # define XPAR_UARTNS550_0_CLOCK_HZ (66000000L) / * 66 MHz clock * / #define XPAR_UARTNS550_1_DEVICE_ID 21 / * Device ID for instance * / # define XPAR_UARTNS550_1_BASEADDR 0xA0000000 / * IPIF base address * / # define XPAR_UARTNS550_1_CLOCK_HZ (66000000L) / * 66 MHz clock * / / ************************************************** *************************** * * UARTLITE Defines. * DeviceID Starts AT 30 * / # define xpar_xuartlite_num_instances 1 / * Number of Instances * / #define XPAR_UARTLITE_0_DEVICE_ID 30 / * Device ID for instance * / # define XPAR_UARTLITE_0_BASEADDR 0xA0020000 / * Device base address * / # define XPAR_UARTLITE_0_BAUDRATE 19200 / * Baud rate * / # define XPAR_UARTLITE_0_USE_PARITY XFALSE / * Parity generator enabled * / # define XPAR_UARTLITE_0_ODD_PARITY XFALSE / * Type of parity generated * / # define xpar_uartlite_0_data_bits 8 / * data bits * // ******************************************* ******************************************* * * ATM Controller Defines. * DeviceID Starts at 40 * / # define xpar_xatmc_num_instances 1 / * Number of Instances * / #define XPAR_ATMC_0_DEVICE_ID 40 / * Device ID for instance * / # define XPAR_ATMC_0_BASEADDR 0x70000000 / * Device base address * / # define XPAR_ATMC_0_DMA_PRESENT XFALSE / * Does device have DMA? * / / ************************************************** *************************** * * Serial Peripheral Interface (SPI) Defines. * DeviceID Starts at 50 * / # define xpar_xspi_num_instances 2 / * Number of instances * / #define XPAR_SPI_0_DEVICE_ID 50 / * Device ID for instance * / # define XPAR_SPI_0_BASEADDR 0x50000000 / * Device base address * / # define XPAR_SPI_0_FIFO_EXIST XTRUE / * Does device have FIFOs? * / # define XPAR_SPI_0_SLAVE_ONLY XFALSE / * Is the device slave only? * / #define xpar_spi_0_num_ss_bits 32 / * Number of slave SELECT BITS * / #define XPAR_SPI_1_DEVICE_ID 51 / * Device ID for instance * / # define XPAR_SPI_1_BASEADDR 0x50000100 / * IPIF base address * / # define XPAR_SPI_1_FIFO_EXIST XTRUE / * Does device have FIFOs? * / # define XPAR_SPI_1_SLAVE_ONLY XFALSE / * Is the device slave only? * / # n u s slave select bits * // ******************************************* **************************************** * * OPB Arbiter Defines. * DeviceID Starts AT 60 * / # define xpar_xopbarb_num_instances 1 / * Number of instances * / #define XPAR_OPBARB_0_DEVICE_ID 60 / * Device ID for instance * / # define XPAR_OPBARB_0_BASEADDR 0x80000000 / * Register base address * / # define XPAR_OPBARB_0_NUM_MASTERS 8 / * Number of masters on bus * / / ************************************************** *************************** * * Watchdog Timer / TimeBase (WDTTB) Defines. * DeviceID Starts AT 70 * / # define xpar_xwdtb_num_instances 1 / * Number of instances * / #define xpar_wwttb_0_device_id 70 / * device id for instance * / # define xpar_wdttb_0_baseaddr 0x70800040 / * register base address * / / ************************************************** *************************** * * Timer Counter (TMRCTR) Defines. * DeviceID Starts AT 80 * / # define xpar_xtmrctr_num_instances 2 / * NUMBER OF Instances * / #define XPAR_TMRCTR_0_DEVICE_ID 80 / * Device ID for instance * / # define xpar_tmrctr_0_baseaddr 0x70800100 / * register base address * / / ************************************************** *************************** * * IIC defines. * DeviceID Starts at 90 * / # define xpar_xiic_num_instances 2 / * Number of instances * / #define XPAR_IIC_0_DEVICE_ID 90 / * Device ID for instance * / # define XPAR_IIC_0_BASEADDR 0xA8000000 / * Device base address * / # define XPAR_IIC_0_TEN_BIT_ADR XTRUE / * Supports 10 bit addresses * / # define XPAR_IIC_1_DEVICE_ID 91 / * Device ID for instance * / # define XPAR_IIC_1_BASEADDR 0xA8000000 / * Device Base Address * / # define xpar_iic_1_ten_bit_adr xtrue / * supports 10 bit addresss * / / ************************************************** *************************** * * Flash defines. * DeviceID Starts AT 100 * / # define xpar_xflash_num_instances 1 / * Number of instances * / # define xpar_flash_intel_support / * include intel flash support * / #define XPAR_FLASH_0_DEVICE_ID 100 / * Device ID for first instance * / # define XPAR_FLASH_0_BASEADDR 0xFF000000 / * Base address of parts * / # define XPAR_FLASH_0_NUM_PARTS 2 / * Number of parts in array * / # define XPAR_FLASH_0_PART_WIDTH 2 / * Width of each part in bytes * / # define xpar_flash_0_part_mode 2 / * Mode of Each Part in Bytes * / / ************************************************** *************************** * * GPIO Defines. * DeviceID Starts AT 110 * / # define XPar_xgpio_num_instances 1 #define XPAR_GPIO_0_DEVICE_ID 110 / * Device ID for instance * / # define XPAR_GPIO_0_BASEADDR 0x90000000 / * Register base address * / # define XPAR_GPIO_0_INTERRUPT_PRESENT 0 / * Interrupts supported? * / # define XPAR_GPIO_0_IS_DUAL 0 / * Dual channels supported? * / / ************************************************** *************************** * * EMC Defines. * DeviceID Starts AT 120 * / # Define XPar_xemc_num_instances 1 #define xpar_emc_0_device_id 120 / * device ID for instance * / # define xpar_emc_0_baseaddr 0xe0000000 / * register base address * / # define xpar_emc_0_num_banks_mem 3 / * Number of Banks * / / ************************************************** *************************** * * PLB Arbiter Defines. * DeviceID Starts AT 130 * / # define xpar_xplbarb_num_instances 1 #define XPAR_PLBARB_0_DEVICE_ID 130 / * Device ID for instance * / # define XPAR_PLBARB_0_BASEADDR 0x300 / * Register base address * / # define XPAR_PLBARB_0_NUM_MASTERS 1 / * Number of masters on bus * / / ************************************************** **************************** * * PLB to OPB Bridge Defines. * DeviceID Starts AT 140 * / # define xpar_xplb2op_num_instances 1 #define XPAR_PLB2OPB_0_DEVICE_ID 140 / * Device ID for instance * / # define XPAR_PLB2OPB_0_DCR_BASEADDR 0x0 / * DCR Register base address * / # define XPAR_PLB2OPB_0_NUM_MASTERS 1 / * Number of masters on bus * / / ************************************************** *************************** * * OPB to PLB Bridge Defines. * DeviceID Starts AT 150 * / # define xpar_xopb2plb_num_instances 1 # define xpar_xopb2plb_any_opb_reg_intf / * Accessible from OPB, NOT DCR * / #define XPAR_OPB2PLB_0_DEVICE_ID 150 / * Device ID for instance * / # define XPAR_OPB2PLB_0_OPB_BASEADDR 0x0 / * Register base address * / # define XPAR_OPB2PLB_0_DCR_BASEADDR 0x0 / * DCR Register base address * / / ************************************************** *************************** * * System ace defines. * DeviceID Starts AT 160 * / # define xpar_xsysace_num_instances 1 #define XPAR_SYSACE_0_DEVICE_ID 160 / * Device ID for instance * / # define xpar_sysace_0_baseaddr 0xcf000000 / * register base address * // *********************************** *********************************************************** * * * Hdlc defines. * DeviceID Starts at 170 * / # define xpar_xhdlc_num_instances 1 #define XPAR_HDLC_0_DEVICE_ID 170 / * Device ID for instance * / # define XPAR_HDLC_0_BASEADDR 0x60010000 / * Register base address * / # define XPAR_HDLC_0_TX_MEM_DEPTH 2048 / * Tx FIFO depth (bytes) * / # define XPAR_HDLC_0_RX_MEM_DEPTH 2048 / * Rx FIFO depth (bytes) * / # define xpar_hdlc_0_dma_present 3 / * DMA SG in hardware * / / ************************************************** *************************** * * PS2 Reference Driver defines. * DeviceID Starts AT 180 * / # define xpar_XPS2_NUM_INSTANCES 2 #define xpar_ps2_0_device_id 180 / * Device ID for instance * / # define xpar_ps2_0_baseaddr 0x40010000 / * register base address * / #define xpar_ps2_1_device_id 181 / * Device ID for instance * / # define xpar_ps2_1_baseaddr 0x40020000 / * register base address * / / ************************************************** *************************** * * Rapid Io Defines. * DeviceID Starts At 190 * / # define xpar_xrapidio_num_instances 1 #define XPAR_RAPIDIO_0_DEVICE_ID 190 / * Device ID for instance * / # define xpar_rapidio_0_baseaddr 0x60000000 / * register base address * / / ************************************************** *************************** * * PCI defines. * DeviceID Starts AT 200 * / # define xpar_xpci_num_instances 1 # define xpar_opb_pci_1_device_id 200 # define XPAR_OPB_PCI_1_BASEADDR 0x86000000 # define XPAR_OPB_PCI_1_HIGHADDR 0x860001FF # define XPAR_OPB_PCI_1_PCIBAR_0 0x10000000 # define XPAR_OPB_PCI_1_PCIBAR_LEN_0 27 # define XPAR_OPB_PCI_1_PCIBAR2IPIF_0 0xF0000000 # define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0 0 # define XPAR_OPB_PCI_1_PCI_PREFETCH_0 1 # define XPAR_OPB_PCI_1_PCI_SPACETYPE_0 1 # define XPAR_OPB_PCI_1_PCIBAR_1 0x3F000000 # define XPAR_OPB_PCI_1_PCIBAR_LEN_1 15 # define XPAR_OPB_PCI_1_PCIBAR2IPIF_1 0xC0FF8000 # define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1 0 # define XPAR_OPB_PCI_1_PCI_PREFETCH_1 1 #define x PAR_OPB_PCI_1_PCI_SPACETYPE_1 1 # define XPAR_OPB_PCI_1_PCIBAR_2 0x5F000000 # define XPAR_OPB_PCI_1_PCIBAR_LEN_2 16 # define XPAR_OPB_PCI_1_PCIBAR2IPIF_2 0x00000000 # define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2 0 # define XPAR_OPB_PCI_1_PCI_PREFETCH_2 1 # define XPAR_OPB_PCI_1_PCI_SPACETYPE_2 1 # define XPAR_OPB_PCI_1_IPIFBAR_0 0x80000000 # define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0 0x81FFFFFF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_0 0xF0000000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_0 1 # define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0 1 #define XPA R_OPB_PCI_1_IPIFBAR_1 0x82000000 # define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1 0x820007FF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_1 0xCE000000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_1 1 # define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1 1 # define XPAR_OPB_PCI_1_IPIFBAR_2 0x82320000 # define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2 0x8232FFFF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_2 0x00010000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_2 1 # define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2 1 # define XPAR_OPB_PCI_1_IPIFBAR_3 0x82330000 #define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3 0x8233FFFF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_3 0x00010000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_3 1 # define XPAR _OPB_PCI_1_IPIF_SPACETYPE_3 0 # define XPAR_OPB_PCI_1_IPIFBAR_4 0x82340000 # define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4 0x8234FFFF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_4 0x00010000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_4 0 # define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4 0 # define XPAR_OPB_PCI_1_IPIFBAR_5 0x82350000 # define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5 0x8235FFFF # define XPAR_OPB_PCI_1_IPIFBAR2PCI_5 0x00010000 # define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0 # define XPAR_OPB_PCI_1_IPIF_PREFETCH_5 1 # define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5 1 #defin e XPAR_OPB_PCI_1_DMA_BASEADDR 0x87000000 # define XPAR_OPB_PCI_1_DMA_HIGHADDR 0x8700007F # define XPAR_OPB_PCI_1_DMA_CHAN_TYPE 0 # define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH 11 / ********************************** ****************************************** * * Gemac Defines. * DeviceID starts at 210 * / # define XPAR_XGEMAC_NUM_INSTANCES 1 # define XPAR_GEMAC_0_DEVICE_ID 210 # define XPAR_GEMAC_0_BASEADDR 0x61000000 # define XPAR_GEMAC_0_DMA_TYPE 9 # define XPAR_GEMAC_0_MIIM_EXIST 0 # define XPAR_GEMAC_0_INCLUDE_STATS 0 / ************************************************** *************************** * * TouchScreen Defines. * DeviceID Starts at 220 * / # define xpar_xtouchscreen_num_instances 1 # define xpar_touchscreen_0_device_id 220 # Define XPAR_TOUCHSCREEN_0_BASEADDR 0x70000000 / ************************************************** **************************** * * DDR Defines. * DeviceID Starts at 230 * / # define xpar_xddr_num_instances 1 # define xpar_ddr_0_device_id 230 # define XPAR_DDR_0_BASEADDR 0 # define XPAR_DDR_0_INTERRUPT_PRESENT 0 / * XUTIL_MEMTEST Defines * / #define XUT_MEMTEST_INIT_VALUE 1 / ** @name Memory subtests * @ {* // ** See the detailed description of the subtests in the file description. * / # Define XUT_ALLMEMTESTS 0 # define XUT_INCREMENT 1 # define XUT_WALKONES 2 # define XUT_WALKZEROS 3 # define XUT_INVERSEADDR 4 # Define XUT_FIXEDPATTERN 5 # define XUT_MAXTEST XUT_FIXEDPATTERN / * @} * / / ***************** Macros (Inline functions) definitions ****************************** / / ****************************************************************************************************************************************************************************************************** ********* / / * Xutil_memtest prototypes * / XStatus XUtil_MemoryTest32 (Xuint32 * Addr, Xuint32 Words, Xuint32 Pattern, Xuint8 Subtest); XStatus XUtil_MemoryTest16 (Xuint16 * Addr, Xuint32 Words, Xuint16 Pattern, Xuint8 Subtest); XStatus XUtil_MemoryTest8 (Xuint8 * Addr, Xuint32 Words, XUINT8 PATTERN, XUINT8 SUBTEST;
