Rules Project: A relatively smart Makefile Writing
Makefile of the project, by the way, it is simply summarized as follows. This kind of writing is relatively halo, the defined rules and many macro are more likely to be a bit tired.
But if the project is relatively large, this way of writing facilitates the unified project generation rules (the same type of files are used with the same processing rules), reducing the workload written by Makefile (do not need to write rules, only need to provide a list of files), It also reduces the probability of error. Compare specifications and flexible and universal, it is worth reference.
This way of writing makes Makefile into a general rule definition file and engineering definition file.
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[COM.MK General rule definition file]
CC = GCC
# .Suffixes defines the type of extension file that meets the compilation rules, .c / .h / .cxx has been supported by default.
# 图 例 增. (Pro * C file. PC can also be processed)
.Suffixes: .d
# Define the unified rules corresponding to the same type of file. CO: # Define how to generate .o rules @echo '-' $ *. C # write this line, you can print the processed file $ (cc) - o $ *. o -C $ *. c # generation .o's statement
.dc: # Define how to generate .C files from .d files @echo '-' $ *. d # write this line, you can print out the filed file CP $ *. D $ *. C # generation. The statement of the C file. DO: # Defines how to generate .o file from .d file rules @echo '-' $ *. d # write this line, you can print the processed file CP $ *. D $ *. C # Because this example is to call the C compiler, it is. C file $ (cc) -O $ *. o -C $ *. C #, generate it from .C file .o
# Define Compile Entry All: Build
#Ne. This sentence defines which source files (CFILE / DFILE defined list) # and what rules (.c = .o are generated from .o; .o; .d = .o) Representation from .d. O ) Generate a target file
Allobjs = $ (cfile: .c = .o) $ (dfile: .d = .o)
# Compile command, indicate the first compilation of the target object, then output the executable (EXE): $ (allobjs) $ (cc) -o $ @ $ (allobjs)
# Clear the statement, which is also utilized using rule definitions, Clean: RM -F $ (DFILE: .D = .o) $ (dfile: .d = .c) RM -F $ (cfile: .c = .o) RM -f $ (EXE)
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[Project Definition File in Makefile Code]
# Define Output Target Name EXE = TESTEXE # The following only need to provide a file list and define compilation CFILE = MC # Defines the C source file list, there can be multiple DFILE = Testd.d Teste.d # Define D Source File list, you can have Multiple
# Assign the compile entry Build: $ (exe)
Commpath =. / # Specify the path of the template
INCLUDE $ (CommPath) /com.mk # contains universal template files, Make will call the rules in the generic template to compile
