source:
Linuxeden
When developing a large system, the program is often divided into many modules. There is a variety of dependencies between each module, usually using makefile in UNIX. Makefile is actually very complicated, I recommend it to you by Stallman Write The manual, there is the most detailed description. Here only to say some of the most common functions. First, an example: AC BC two programs. AC EXTERN VOID P (Char *); main () {p ("Hello World ");} BC #include
Void P (Char * STR)
{
Printf ("% SN", STR);
}
Makefile
Hello: a.c B.c
GCC a.c B.c -o hello
----
Here is a Tab (note must have a Tab)
Make
GCC a.c B.c -o hello
Generate an executable called Hello.
Makefile is composed of rules, each rule has three parts: target (dependency), dependency and command (Command). In the above example, Makefile only has a rule, its goal is Hello, and the period is dependent AC BC, its command is GCC AC BC -O Hello.
Depending on the target of another rule, it can also be a file. Each rule is handled like this. If the target is a file is: When its dependence is a file, if the dependent time is new, the rule is included in the rule. The command to update the target; if the dependence is another goal, the same method is used to process this goal first. When the target is not an existing file, it must be performed.
E.g:
Makefile
Hello: a.c B.O
GCC a.c B.O -O Hello
B.O: B.C
GCC B.C -C
When running Make, you can connect a target name as a parameter, indicating to handle the change target. If there is no parameter, the first goal is handled. The last example is executed, it is to process the Hello target. Hello relies on file AC and Another target Bo, first deal with Bo, call GCC BC -C to update the BO, then return, call GCC AC Bo -o Hello to update Hello.
Define variables:
You can define your own variables in makefile, for example:
CC = GCC
Hello: a.c B.c
$ (Cc) a.c B.c
Special variable:
$ @ 目 名 名字
$ $ ^ All dependence $? Relation of all the goals Default rules: Make I have some default methods to handle the files it encounter. Such as: Makefile Hello: a.o B.O GCC A.O B.O -O Hello Make GCC a.c -o a.o GCC B.C -O B.O GCC A.O B.O -O Hello Make automatically calls GCC to compile A.O and B.O. However, the problem is that we often change the default rules. If we want to add parameters -g to add debugging information. Use the following method: % .O:%. c GCC-C $ <-g -o $ @ Where% is a wildcard. Pseudo-target: .Phony: Target Commands of pseudo-target will be executed. E.g Clean: RM A.O B.O The purpose of Clean is simple, just to delete all the .o files. But write, if you are in a file called Clean, you will have a problem. Plus the following line: .Phony: Clean Make Make know this is a pseudoactor. Set the search path E.g: ~ / program / a.c ~ / program / include / a.h Makefile vpath% .h incrude A.c: a.h Make first looks in this directory, then find it under the directory specified by VPath. In this case, Files with .H-bit extensions will be found in ~ / program / include /. A slightly complex example: a.h a.c B.H B.C Makefile Objects = a.o B.O # Used compiler CC = GCC # Desired parameters Flags = -g # To connect the library LIB = -lcrypt A.c: a.h B.C: B.H # .o file automatically relies on .c file. % .O:%. c GCC -C $ <-o $ @ $ (flags) $ (lib) All: $ (Objects) GCC $ (Objects) -o Hello .Phony: Clean Clean: RM $ (Objects) When you perform Make, first, make for gnumakefile, if you don't find Makefile, let's finalize makefile. But for compatibility considerations and your eye, you can usually use -f filename to specify. Make's common parameters: -k ignores errors and continues to run. -C DIR is done in DIR.
