GNU Make is an Make tool for development source code. What is MAKE? People who write programs in the command line should know that it is a project management tool. Its most basic use is the compilation and connection of the management project. It will follow rules (defined in rule files), depending on the order to compile, connect, or install them into the system. GNU Make's executable usually is make.exe. A simple example - Basic Rules Let's take a simple example (the following content is used as an example of the Win32 platform): file name: makefile1. # Makefile2. # This is a example of make file3. All: A1 a24. @Echo this IS all! 5. A1: 6. @echo this is a1! 7. A2: 8. @echo this is a2!
After running Make, the results are as follows: this is a1! This is a2! This is all!
Let us now analyze this simple rule file. On the 1st, 2nd lines don't say, you can see that it is a comment. In the Make rule file, the comment is the same as "#", which is the line comment, and "//" function in C . However, you can't put it behind other statements, you will be wrong. The third line is the rule start! All: A1 A2, the name of the rule is all, which is usually a target name. One rule can have a name, like this, you can also write it into all all2: a1 a2. At this time, the rules have two names-AlL and ALL2. Of course, there can be more, see yourself. The next 5, 7 lines are also the start of two rules. After ":", it is dependency. In this line, there are two dependencies, namely A1 and A2, respectively. These dependencies can be other rule names (target names), or the file name. The relationship between dependence and the target is "dependency". In a rule, there can be zero (like two rules behind), one or more dependencies. Chapter 4 @echo this is all! Is the command line. It is the command to execute when executing all rules. It is to be noted that the command within a rule is to start with a line of tab to indicate that the command belongs to a rule. A rule can also have multiple commands, each command occupies a row (starting with Tab). As for which commands can be used, this is entirely on the OS and Shell you use. When Make is executed, it will find the first rule. Then Make will check the relationship between dependence and goals. If the target is longer than the old, the rule is executed to update the target. End of the regular execution. How to determine the goals and relying on the new and old? If the target (file) does not exist, the target time is 0; if the target (file exists), the target time is the modification time of the file. If the dependency is a rule, the rule of the execution (here is a recursive), then the time dependent is the current latest time; if it is an existing file, it is the modification time of the file, otherwise an error. After that, the relationship between the goals and dependencies can be compared. However, a little particular is that the dependent time is 1 when there is no dependency. In this example, Make first finds the rule "all", discover the target does not exist, so the target time is 0; then lookup "A1", the result "A1" does not exist; so, the rule "A1" is executed. "A1" does not exist, so its time is 0, and "A1" does not depend on, its dependency time is 1; 1> 0, so the rule "A1" is executed. Then return the rule "all" and check depending on "A2". "A2" execution process is the same "A1". At this time, "all" target time is 0, dependent time is the latest time. So, execute the command "all" command. Of course, everyone can specify a rule to let Make execute, such as: make a1 this command is to tell the Make program not to find the first rule, but the rule "A1" is executed. And we can also perform multiple rules at a time, such as: executing Make A1 A2 will continue "A1", "A2" two rules. OK, although it is very confusing, I also cost me for a long time. Everyone should have a little understanding of the implementation of the Make rule. Now summarize the dependencies.
The following (the content in brackets is optional): target: [dependence] [Dependence2] [...] [command] [command2] [...] target can be a file name. Dependence can be other Target names or file names. Command is the command line running by the operating system. Variables A Make rule file has these contents that have been basically working. However, when we are compiling a program, if some content should be used repeatedly, it is very troublesome every time you write a long string. As a result, Make introduces this concept (actually seeing as a simple scripting language). The definition of macro variable is as follows: var1 = this is a macro demo! Var1 is the variable name, its value is "this is a macro demo!" If we want to use this variable value, then the operator is only line- $ (Var1) representative is "this is a macro demo!". As follows Makefile1. Var1 = this is a macro demo! 2. All: 3. @Echo $ (var1) result output: this is a macro Demo! User can define macro variables when performing a command line. The form is as follows: make all var1 = "this is a test" execution result is: this is a test We not only use custom variables, but also use system environment variables in this way. This makes it possible to make it easy for us to recommend flexible rules. The result is as follows: 2. @Echo $ (WINDIR) execution result is: C: / Winnt (Note: Makefile is sensitive) In addition, there are some constant specific variables in Makefile. These variables can replace the goals, dependencies, etc. in different rules. Make the rules to build more convenient. Please see the following example: 1. All: a.exe2. A.exe: a.obj3. CL $
Target type
Dependency type
command
C procedure
* .o
* .c
$ (Cc) -c $ (cppflags) $ (cflags)
C program
* .o
* .cc
$ (CXX) -C $ (CPPFLAGS) $ (CXXFLAGS)
Assembler
* .o
* .S
$ (As) $ (asflags)
Frotran
* .o
* .f
$ (Fc) -c $ (fflags)
Pascal
* .o
* .p
$ (Pc) -c $ (pflags)
connection
* .out
* .o
$ (CC) $ (LDFLAGS) Name.o $ (LOADLIBES) $ (LDLIBS)
You can see that there are a lot of different macros in this table. These macros are built in the compiler, and we can also modify them manually, so that you can achieve the modification of the built-in rules.
Please see the following Makefile:
CC = GCC
2. A: A.O
Oh, isn't it very strange? Nothing, I only wrote a rule without content, how can I run? Try it! The results are as follows:
gcc -c -o a.o a.c
GCC A.O -O A
In the first line, I changed the value of the built variable CC to GCC (default CC). This way, when compiling, use the GCC I set. On the second line, I gave target a and dependence A.O. Because there is a default rule from A.C to A.O, if you have a.c file, Make will automatically use the built rules to compile. Everything is OK!
Other rules You can also try it.
In addition to this traditional rule, there is a built-in rule, a suffix rule. Please see the following Makefile:
A.EXE: A.O
2. CL A.O / MD / NOLOGO
3. .c.o:
4. CL $ ^ / c / fo $ @ / md / nologo
In this rule file, no explanation A.O is generated by a source file, only gives a .c.o's strange rule. This rule means that it is generated with the corresponding .C source program for the target of .o as the extension. The resulting command is the command given in the rule.
Of course, Make does not contain all available extensions. It contains the extensions that are usually used .c, .o, .s, .cc and other unix. Under Windows, we have to add a few names manually, otherwise it is not very convenient. To add an extension, you will be done by .SUFFixes. For example, I have to add .asm and .inc these two extensions. Just add .Suffixes .asm .inc in Makefile.
Other built-in rules, you have to try it yourself, not to explore it, it is difficult to master!
Commonly used parameters
The previous introduction of the WI written method of Makefile is now speaking, the basic parameters of the Make program are now.
-f parameter can specify the name of the makefile, so you can use Makefile as the name of the rule file.
The -i parameter allows the Make program to ignore the runtime error and continue to run.
The -v parameter is used to display the version number of the Make program.
--Help parameters can display the parameters of the Make program.
Ok, I just say these four most common parameters! Other parameters, everyone to explore! Write an afternoon, the head is big! Also, this is just a entry. Make also has more complex control statements and some functions, free to write! The friend who wants to learn is best to go to the GNU website to find a document, learn!
Finally, give everyone some resources, you can find GNU Make. Http://sourceforge.net/projects/mingWhttp://www.cygwin.com/
