http://blog.9cbs.net/jasonme/archive/2005/02/02/277174.aspx
One. Overview
two. Dependency check: Make vs. angle
three. Implicit rules basic usage
four. Dependence
Fives. Empty rule
six. Special goal
Seven. Unknown target
Eight. Make's reserved word
nine. Quietly run commands
ten. Automatically restore SCCS files
eleven. Passing parameters: Simple Make Macro
First.
We will introduce your make programs, which will include: hidden dependency check command-dependent check mode matching rules Automatic Repair Source Code Control System (SCCS) file
This version of Make can work normally with the previous version of Makefile. Depending on the enhanced version of Makefile may not be compatible with other versions of Make applications. (Make's Enhancement See Related Information) Make organizes the process of generating target files and executables. It allows the compiler to be eliminated unnecessary recompilation for different modules that have not been affected after the code is changed. Make makes the process of compilation more simplified. You can also use it from moving any complex or duplicated non-interactive work. You can also use make to update and maintain target library files, run test tools, or install files to file systems or tape.
Work with the Automatic Repair Source Code Control System (SCCS), you can use Make to ensure a large software project can compile the version you want to get according to the source code of the entire system. Make reads information from a file called Makefile called Makefile, which includes what files you want to compile in the compilation process, and how to compile them. When you have finished writing and tested Makefile, you can don't have to take into account the details of the compilation process.
two. Dependency check: Make vs. angle Operation Although scripts can be guaranteed in some very subtle situations, it is usually not suitable for compiling a software project with scripts. On the one hand, you can't be changed when a program or module is changed, waiting for a simple script to recompile each program or target module. On the other hand, since each iteration has to be edited to edit the script is contradictory with the goal of consistency. Although it is possible to recompile the modules that need to be compiled with a very complex script, Make will make this matter better.
Make allows you to write a simple and structured list with compiled content with compilation. It uses a dependency check mechanism to compare the source file or module of the intermediate file obtained by the source file. Make only recompiles these modules only after one or more pre-translational premise files are compiled last time.
Make compares the final modification of its dependent file to determine whether a target file has expired for its dependencies. If this module does not exist, or the module is earlier than its dependency file generated, Make thinks that this module file is expired, so it is recompiled it through the corresponding command. A module can be considered expired when compiling the command to generate its commands.
Because Make is a completely dependent scan, modification of a source file will consistently affect any number of intermediate files or processing procedures. This allows you to specify a step of top-down hierarchy. You can imagine Makefile into a recipe. Make reads the recipe, decides which steps need to be executed and only perform the steps required for manufacturing the final module. Each file to be compiled, or the step of executing is called a target. Makefile includes its name including its name, which depends on the file list and a series of compiles to generate this target.
This series of commands are called rules. Make regards dependencies as the goal of prerequisites, updating them before processing current goals (in need). The rules of a goal are not necessarily to generate a file, but if it generates a file, it is called the target file. Each file generated by the target (for example, the file depends on the target) is called the dependencies. If the name is not generated with the name of a target, then make the rules and think that the target is the following operation. It is up-to-date. Make assumes that only the file currently being processed may be modified. If a source file is being modified by another process when it is operated by the Make, it is possible to be in an inconsistent state. Write a simple makefile for a target item, Makefile's basic format is: target ...: [dependency ...] [command] ....
At the first line, the target name list ends with a colon. It's a series of dependencies (if any). If several goals are listed, this indicates that each such goal is compiled separately with the rules provided. The later lines started in tab, such starting is considered to be a command line containing the target. There is a very common error that uses space instead of Tab, causing a write method for the Makefile file.
Start with "#" until the row that the next new row started is considered a notes, it will not cause the end of a target item. The target term is the following non-empty and end of the row mark started in non-Tab or #, or is identified by the file end.
A small Makefile can be composed of only one goal, such as: Test: Ls Test Touch Test
When you don't have a mak command, it will automatically find a file called "makefile" to compile. If it does not exist, "makefile" will be found. If these files are not under SCCS control, Make checks its historical file to determine makefile. If this is already expired, Make will get the latest version.
If Make finds a Makefile, it starts to rely on the first target entry that appears in Makefile. Otherwise, you have to list the target to be compiled in the form of a parameter in the command line. Make will display all its running commands in the process of constructive goals. Such as: $ MAKELS TestTest Not FoundTouch Testls Testtest
In this example, because the Test file does not exist, it is considered to be expired, and make the rule in the target item. If you follow Make again, it will tell you that the goal is already the latest, so you skip the execution of the rules. Such as: $ Make'Test 'is up to date.
Note --- If the command line contains any housing original characters, such as a semicolon (re-symbol <,>, >>, |), instead (*,?, [], $, =) Or reference , Exit or comments (", ',,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
There is a very special nature of different two lines in a rule. The different command line is performed under different processes or shells. This means that such as the following Makefile: Test: CD / TMP PWD execution results may be What you think is different, its result will be: $ make test / tmpwd / usr / tutorial / waite / arcana / minor / pentangles instead of what you think should be / TMP
You can use the semicolon to indicate that the command is performed in a separate shell, such as: test: CD / TMP; PWD or you can also position the command input stream to the next row with the '' character in Makefile . The new line is viewed by Make as a space. The reverse slope must be the last character of a row. The semicolon must be there in the shell. Such as: Test: CD / TMP; PWD 3. The basic usage of implicit rules: When there is no rule for a specific point, make attempts to build it with an implicit rule. When Make finds a rule of a class of files belonging, it will be used in this implicit rule.
Outside all your Makefile you wrote, Make will continue to read into a default makefile, which is located in /usr/share/lib/make/make.rules, which contains some hidden rules of the target item, and some other information .
Note - The hidden rule is manually prepared manually in the early Make. There are two types of implicit rules: the suffix name and pattern matching. For different files with another file, the following names have different files, the suffix rules indicate a series of commands to compile this file according to this suffix name. Mode matching rules are based on a target with dependencies and Wild-Card mode to select compilation rules. Such implies rules are default the suffix name rules. In some cases, use the hyperfix rule to eliminate the trouble writing a whole makefile file.
For example, through a separate functions.c C language file to build a target file named functions.o, you should use the following command: $ make functions.occ -c functions.c -o functions.o This rule Since the source file Nonesuch.c is also valid for the NoneSuch.o target file. To build an executable named Functions (which does not have a suffix name) from functions.c (it does not have the following command: $ make functionscc -o functions functions.c This rule is called the rule of AC. Co suffix Name rules (pronounced-see-dot-oh "). This rule is called .c rule for building an executable program from A.C.
four. Dependence:
After the beation begins, it processes the target by depth dependence on the pre-priority rule. For example, as the following Makefile: Batch: a b Touch Batchb: Touch Ba: Touch AC: Echo "Won't see me" be started from the target Batch. Because Batch has some dependencies yet have not been checked, they are A and B, and make delay generate BATCH until it checks the dependence rules of A and B. BATCHA B is dealing with it because A is not dependent. If the file does not exist, the make will execute the rules in the target item. $ MakeTouch a ..... Next, make back to the parent target Batch, because there is still a target B without checking dependencies B, and make starts to find B dependence. ..... Touch B ..... Finally, because all Batch's dependencies have been checked and have been built (if needed), Make generates Batch: batch
Because it reconstructs at least one BATCH dependency file, Make assumes that Batch has expired, and rebuild BATCH, if A or B is currently not constructed, but in the current directory, it has been updated, MAKE Time Edition Comparison also makes BATCH to be rebuilt: ..... Touch Batch does not have been processed in the dependent scan. Although there is a target item on C, it has not been executed in the Makefile. You can choose an instead of starting target, such as passing C to make in the form of a parameter. In the next example, the Batch target does not generate a file, replaced by it, is used as a tag of a group of targets.
BATCH: A B CA: A1 A2 Touch AB: Touch BC: Touch CA1: Touch A1A2: Touch A2 In this case, the targets are checked and processed in the following order: BATCHA B CA1 A2
In essence, make next: 1. Check the Batch's dependence, pay attention to the three sub-targets, so you will postpone BATCH generation 2. Check A, this first dependency target, notice that it has two own dependence objectives , As an example, make will continue: a. Check A1, re-construct it if needed. B. Check the A2, re-construct it if needed. 3. Decide whether to rebuild the A4. Check B and rebuild it when needed. 5. Check C and rebuild it when needed. 6. After traversing its dependent tree, Make checks and handles the top target BATCH. If the BATCH has other rules, make will execute it. Here Batch does not have other rules so Make does not perform any operation, but pay attention to the BATCH has been rebuilt, and any target dependent on BATCH will be rebuilt.
Fives. Empty rules: If a target item is not ruled, make will try to build it from a hidden rule. If Make does not find a suitable hidden rule to handle it, and the corresponding rules are found in the SCCS history, Make will think that the target does not have the corresponding file, which refers to this deletion rule as an empty rule.
Note - You can use an empty rule dependence to force the target rule to be executed. A more convenient call for this situation is forced. For the following Makefile:
Haste: Force Echo "Haste Makes Waste" Force: Make will operate under the rules, even when this file is already the latest, no exception: $ Touch Haste $ make Hasteecho "Haste Makes Waste" Haste Makes Waste
Make has many built-in special targets to reach a lot of special features. For example,: .precious target will guide your Make to the reserved library file after Make is interrupted.
six. Special goals: 1. Start 2 in "." 2. There is no dependency 3. You can appear in any of the Makefile.
Seven. Unknown Target: If the name of a file is not in the command line, it is not in the dependencies list, and it: 1. It is not a file in the current working directory. 2. It doesn't have a target and dependencies 3. It does not belong to any file class defined by hidden rules 4. No SCCS history file 5. There is no ./Default Special Target Definition Rule This Make will stop running and issue an error message.
As: $ Make Believemake: Fatal Error: Don't know '. Note - Although if the -k parameter works, Make will continue to target other targets that do not occur with this error. Operation.
Duplicate target: The target can appear more than once in a makefile, such as: foo: DEF_1FOO: DEP_2FOO: Touch Foo: Foo: Dep_1 dep_2 Touch foo is exactly the same. However, many people think that if a goal will only have a good time, this is relatively easy to read.
Eight. make reserved words: .BUILT_LAST_MAKE_RUN .DEFAULT .DERIVED_SRC .DONE .IGNORE .INIT .KEEP_STATE .MAKE_VERSION .NO_PARALLEL .PRECIOUS .RECURSIVE .SCCS_GET .SILENT .SUFFIXES .WAIT FORCE HOST_ARCH HOST_MACH KEEP_STATE MAKE MAKEFLAGS MFLAGS TARGET_ARCH TARGET_MACH VERSION_1.0 VIRTUAL_ROOT VPATH
nine. Quietly run the command: You can add a "@" limit to the rule of the rule to display data for display data. For example, as the following goals: quiet: @echo you only see me once The following effects: $ make Quietyou Only See Me Once If you want to limit the display in a specific Make run, you can use - s parameters. If you want to limit all commands to select the display, you need to join .slient in your makefile. Such as: .slientquiet: echo you. Only See me once
The specific function target is "." As the beginning. The target name is in a ".", The target starting will never be used as a start-up goal unless it is specified as a parameter that is required for the command line. Make only outputs an error message and stops when the command returns a non-0 exit command. For example, if you have a goal: RMXYZ: RM XYZ and there is no file named XYZ below the current directory. Make hangs after the RM returns its error status value. $ LS XYZXYZ NOT FOUND $ MAKE RMXYZRM XYZRM: XYZ: No Such File or Directory *** Error Code 1make: Fatal Error: Command Failed for Target 'RMXYZ' Note - If - and # is the first two characters, they will play Effect. Continue to proceed to the exit code of the command, you can use a "-" as the first non-Tab character: rmxyz: -rm xyzrm: xyz: no sudh file or directory *** error code 1 (ignored)
Note - Unless you test a Makefile, in the global situation, it is a bad idea to ignore non-0 errors.
Although it is recommended to do this, you can ignore all the error code through the -i parameter. You can also ignore all exit code by including .ignore this special goal in Makefile, although such processing should be avoided.
If you are processing a list of targets, and you want Make to continue the next goal, you can use the -k parameter.
ten. Automatically restore SCCS files: When the name of the source file is in the dependencies list, Make will treat them like other goals. Because the source file is assumed to exist in this directory, there is no need to add a directory item in Makefile. When a goal does not matter, it exists in the current directory, make the file is already the latest. However, if the source file is controlled by SCCS, Make will make some additional checks to ensure that this source file is the latest. If the file does not exist, or the history file is updated, then make automatically restores the latest version of the file: sccs get -s filename -gfilename Note - In other versions of Make, automatic SCCS recovery is only a few A feature of a specific hidden rule. Moreover, with the previous version of Make, MAKE looks for historical files in the sccts directory; the historical documents in the current directory are ignored. However, if the source file is writable for anyone, Make will not restore a version of the update. $ Ls sccs / * sccs / s.functions.c $ rm -f functions.c $ make functionssccs get - S Functions.c -gfunctions.ccc -o functions functions.c
Make checks the timestamp of the recovery version of the historical file and the timestamp of the historical file. It does not check if it is the latest version under the current directory. In this way, if Which person is taken at a time to take an operation (SCCS Get -C), Make will not find this fact, and you will unintentionally build an older version of the target file. In order to ensure that your compilation is the latest version, you should get SCCS or an SCCS clear command before Make, with SCCS or an SCCS clear command.
The command to restore the SCCS recovery SCCS file is specified in the default Makefile. SCCS_GET is specified. In order to prohibit automatic recovery, it is possible to add an empty rule in the corresponding target item in makefile.
# 禁 s SCCS recovery .sccs_get
eleven. Passing parameters: Simple Make Macro Macro Replacing When you want to pass parameters from Makefile to command to exercise your work is very easy. Suppose you have to compile a optimized version of your program and use the cc -o parameters. You can reach this nature by adding Make macro to makefile, such as the following example: functions: functions.c cc $ (cflags) -o functions functions.c
The macro introduces the character appearing in the role of a value of the placeholder, or in the Makefile itself, or a parameter as a Make command. If you can define a cflags macro, make will switch your prior defined macro to the specified location.
$ RM Functions $ make functions "cflags = -o" cc -o -o functions functions.c Note - There are CFLAGS introduction in .c and .c.o implicit rules. Note - The command line definition must be a single parameter, so this reference is as follows: If a macro is not defined, make will extend such a reference to an empty string, you can also define one in Makefile Macro. A typical application is to set CFLAGS to -o so that an optimized target code can be generated by default .cflags = -ofunctions: functions.c cc $ (cflags) -o functions functions.c
A macro defined in the command line argument overrides the macro defined in Makefile. Conditional definition macros is the exception of this rule.
For example, when compiling a function module that is debugging with DBX or DBXTOOL, you can define cflags in the command line to -g: $ rm functions $ make cflags = -gcc -g -o functions functions.c GPROF to compile an external variable, give the -O and -PG simultaneously to CFLAGS. A macro reference is no longer a single character, and must contain parentheses. If the macro name is just a character, the parentheses can be ignored. You can replace parentheses with curly brackets. For example, '$ x', '$ (x), and' $ 'is exactly the same.
