Variety of precision timing programming methods for single-chip timing interrupts
Author: ■ Nanjing Agricultural University
Speech
The interrupt response delay time of the MCS-51 single-chip microcomputer depends on whether or not other interrupt service programs are performed, or depending on what instructions being executed. The interrupt response time in a single interrupt system is 3 ~ 8 machine cycles [1]. Whether it is the error caused by the error, in the precise timing, the effects must be considered to ensure precise timing control. Depending on the different application of timed interrupt, different precise timing programming methods should be selected.
The timer T1 is operated in the timing method 1 as an example, the crystal frequency is 12 MHz.
1 method 1
When the timer overflow interrupt gets a response, the timer count, read the count value (reflect the delay time of the interrupt response), calculates when it is calculated from the next interrupt according to this count value, thereby reloading and Start the timer. For example, the timing period is 1 ms, the timer is usually reloaded value -1000 (0FC18H). The following program considers 7 machine cycle times between the stop count (CLR TR1) to restart count (SETB TR1) when calculating the precise reload value of each timing period. In the program #LOW (-1000 7) and #high (-1000 7) are assembly symbols, which represent -1000 7 = 0FC1FH this immediate number of low bytes (1FH) and high bytes (0fch).
......
CLR EA; Prohibition of all interrupts
CLR TR1; Stop Timer T1
Mov A, # l (-1000 7); expected low byte
ADD A, TL1;
MOV TL1, A; reloading low bytes
MOV A, # high (-1000 7); Higher byte processing
AddC A, TH1
MOV TH1, A
Setb TR1; restart timer
Setb EA; reopen interrupt
......
This method is suitable for the case of timing errors caused by various reasons.
2 method 2
If the timing period is 10ms, the timer is usually reloaded to 0D8F0H, and the interrupt subroutine is as follows [2]:
Orl TL1, # 0f0h
Mov TH1, # 0D8H
......
Here is the orl TL1, # 0f0h instead of MOV TL1, and the # 0f0h can increase timing accuracy. This method is only applicable to the lower 4 bits of the low-level byte of the load value, and the delay time of the interrupt response is less than 16 machine cycles. Similar timers are reloaded with 0FFF0H, 0FFE0H, and the like.
3 method 3
If the timing period is 1 ms, the timer is usually reloaded value of 0FC18H, and the interrupt subroutine is as follows:
Mov A, # l (-1000 4); expected low byte
Add A, TL1
MOV TL1, A
MOV A, # high (-1000 4); Higher byte processing
AddC A, TH1
MOV TH1, A
Dec TL1; Restore 2 machine cycles in advance
......
In this method, the timer counting process is not stopped. If the instructions ADDC A, TH1 or MOV Th1, A is executed, the value of the TL1 overflow to the TH1 is generated, the value of TH1 is not aligned, and a larger error is generated. . To this end, the program segment is at the beginning of the reload value, and if there is overflow, it can occur in advance, and two machine cycles are considered to reload the TL1 reloaded.
This method is applicable to the case where there is no other higher priority interrupt source in the system. If similar to method 1, the opening and end of the block is added to all interrupts (CLR EA) and the SETB EA) command, they will apply to all situations. 4 method 4
If the timing cycle is uncertain, I only know that the timer reload value is stored in the registers R3, R2, and the interrupt subroutine is as follows:
Mov A, # 05H; 3 machine cycles load TL1, 2 cycles advance
Add A, TL1
Add A, R2
MOV TL1, A
MOV A, R3; processing high bytes
AddC A, TH1
MOV TH1, A
Dec TL1; Restore 2 machine cycles in advance
......
This method is suitable for the case where the timing cycle is uncertain, and the other same method 3.
5 method 5
When the location interrupt occurs, the AJMP $ (or SJMP $) waiting instruction is typically occurred, and the interrupt delay time is 3 or 4 machine cycles. Take a fixed value 4 to simplify the compensation procedure. As an example of timing cycle 1ms, the interrupt subroutine is as follows:
ORG 001BH
MOV TL1, # l (-1000 4)
MOV TH1, # high (-1000 4)
......
This method is applicable to the timing interrupt to occur in the same instruction location, and there is no other interrupt source.
Conclusion
The above five method errors do not exceed one machine cycle, with methods 1, 3, 4 more general, suitable for any case, but the procedure is long; the method 2, 5 is simple, but must pay attention to satisfying the corresponding conditions. Of course, there are other methods [3], but it is more cumbersome, not ideal, and is not included here.
references
1 Sun Hanfang, Xu Aiqing. Principle and Application of MCS-51/96 Series [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 1988
2 weekeep-aircraft application design technology. [M]. Rev.Beijing: Beijing: Beijing University of Aeronautics and Astronautics Press, 2002
3 Nie Yi. Analysis and Compensation of Single Error Timer Interrupt Time Error [J]. Microcomputer Information, 2002, 18 (4): 37 ~ 38
蹇 蹇 亮: Lecturer, mainly engaged in testing measurement technology and microcontroller teaching.
(Required Date: 2004-03-30)
