Whether in Linux or in a UNIX environment, Make is a very important compilation command. Do not
Tube is your project development or install application software, we all often use Make or make install. Profit
With the Make tool, we can decompose large development projects into multiple modules that are easier to manage, for a package
Including hundreds of source files, using make and makefile tools can be simple and bright and geographically smooth.
Complis with complex relationships between parts. And so many source files, if you want to type the GCC command each time
If the translation is translated, it is a disaster for programmers. The Make tool automatically completes compilation, and
You can compile only parts that programmers modified after the last compiled. Therefore, effectively utilizing MAKE and
Makefile tools can greatly improve the efficiency of project development. At the same time, you will not master Make and makefile, you will not
The application software under Linux is no longer.
But unfortunately, there is no detailed introduction to this function in many books that describe Linux applications.
Strong but very complicated compilation tools. Here I will introduce Make and its description files in detail here.
Makefile.
Makefile file
Make Tools The most important feature is to describe the source programs through the Makefile file.
The interrelationship and automatically maintain compilation work. The Makefile file needs to be written, files according to some syntax
Need to explain how to compile individual source files and connect to generate executables, and require the dependence between the source files
relationship. Makefile file is a lot of compilers - including compilers under Windows NT - Maintenance Compilation
Common methods, just modify the Makefile file through the friendly interface in an integrated development environment.
In UNIX systems, use Makefile as a Makfile file. If you want to use it
His files as makefile, specify the makefile file with the Make command options like the following:
$ Make -f Makefile.debug
For example, a program named proga.c, fileb.c, and filec.c, by three progra, fileb.c, and filec.c, and
The library file LS is compiled, and the three files also include their header file A.H, B.H and C.H, respectively. Usually
Next, the C compiler will output three target files filea.o, fileb.o, and filec.o. Suppose Filea.c and
Fileb.c must declare a file named DEFS, but filec.c is not available. That is, in Filea.c and Fileb.c
Have such a statement:
#include "defs"
Then the following document describes the interconnection between these files:
-------------------------------------------------- -------
# It is a example for describing makefile
PROG: Filea.o Fileb.o filec.o
CC Filea.o fileb.o filec.o -ls -o prog
Filea.o: filea.c a.h Defs
CC -C filea.c
Fileb.o: fileb.c B.H Defs
CC-C fileb.c
Filec.o: filec.c c.h
CC-C filec.c
-------------------------------------------------- ------------
This description document is a simple Makefile file.
From the above example notes, the first character is a # 行 注 行 行 行. The first non-note line
The PROG is generated by three target files filea.o, fileb.o, and filec.o link. The third line describes how to
The file-dependent file establishes an executable. The next 4, 6, 8 lines specify three target files, respectively, and what they rely on .c and .h files and DEFS files. The 5, 7, 9 row, specifies how to deserve from the target
Parts established the goal.
When the filea.c or a.h file is modified after compiling, the make tool can automatically recompile
Filea.o, if there is two compilation before and after, Filea.c and A.H have not been modified, and Test.o is still
If you exist, it is not necessary to recompile. This dependency is especially important in program compilation of multi-source files. through
In this definition of this dependency, the Make tool avoids many unnecessary compilation work. Of course, use shell
The script can also achieve the effect of automatic compilation, however, the shell script will all compile any source files, including which
Do not need to recompile the source file, while the Make tool can rely on time and goals of the target last time.
The update time of the source file is automatically determined which source file should be compiled.
Makefile files as a description document generally needed to include the following:
◆ Macro definition
◆ Interdependence between source files
◆ Executable command
Makefile Allows the use of simple macro stem files and related compilation information, in Linux
Model macro is variable. In the reference macro, just add $ symbols before the variable, but it is worth noting that if the length of the variable name
More than one character, you must add brackets () when referenced.
Below is an effective macro:
$ (Cflags)
$ 2
$ Z
$ (Z)
The last two references are completely consistent.
Need not to pay attention to some macro predefined variables, in UNIX systems, $ *, @, $? And $ The value of the special macro will have corresponding changes during the execution of the command, and more booking is defined in GNU Make. Variable variable. Details about predefined variables, Macro definitions allow us to get away from those with long-boring compilation options to write makefile text The piece brings great convenience. -------------------------------------------------- ------- # Define a macro for the object files Objects = filea.o fileb.o filec.o # Define a macro for the library file Libes = -ls # @ use macros Rewrite makefile PROG: $ (Objects) CC $ (Objects) $ (Libes) -o PROG ...... -------------------------------------------------- ------- At this time, if you do a MAKE command without a parameter, you will connect three target files and library files ls; If there is a new macro definition after the make command: Make "libes = -ll -ls" The macro definition behind the command line will override the macro definition in the Makefile file. If LL is also a library file, at this time The make command will connect three target files and two library files LS and LL. There is no clear definition for constant NULL in the UNIX system, so we want to define a NULL string Use the following macro: Stringname = Make command Once the board, not only macro definition can be displayed, but also to other command line parameters, these parameters refers to Set the target file that needs to be compiled. Its standard form is: Target1 [Target2 ...]: [:] [dependent1 ...] [; commands] [# ...] [(Tab) Commands] [# ...] Some of the middle part of square brackets represent options. Targets and Dependents can contain characters, numbers, periods, and "/" symbols. In addition to the reference, Commands cannot contain "#", nor allowing the wrap. In normal case, only one ":" in the command line parameters, at this time, the Command sequence is usually The description of some definition file dependencies in the makefile file is related. If those descriptions associated with the target The row specifies the associated command sequence, then performs these related command commands, even in the semicolon and (tab) The Aommand field behind or even NULL. If those rows related to the target are not specified Command, then the system default target file generation rules will be called. If the command line argument contains two colonies "::", then the Command sequence at this time may be All the lines of the document dependencies in makefile are related. In this case, those description lines related to the target associated Pointed related commands. It will also be implemented in the Build-IN rule. If a non-"error signal is returned when the command command is executed, for example, a Makefile file There is a wrong target file name in the middle, or a command string that makes a character head, Make operation is generally This termination is terminated, but if Make has a "-i" parameter, Make will ignore such an error signal. Make life itself can have four parameters: logo, macro definition, description file name, and target file name. its Standard form is: Make [Flags] [Macro Definitions] [Targets] The flag bit flag option under the UNIX system is: -f file specifies that the file file is a description file. If the file parameter is "-", then the descriptor Parts points to standard inputs. If there is no "-f" parameter, the system will name the default current directory as Makefile or name Makefile's file is description file. In Linux, the GNU Make tool follows in the current working directory. Gnumakefile, Makefile, Makefile searches for the Makefile file. -i ignores the command to perform the error message. -s silence mode, does not output the corresponding command line information before execution. -r prohibits the use of Build-in rules. -N Non-execution mode, output all execution commands, but does not execute. -T update the target file. -q make operation will return "0" or non-"0" status letter based on the target file has been updated interest. -p outputs all macro definitions and target file descriptions. -d debug mode, output detailed information about files and detection time. The common option of the Make flag in Linux is slightly different from the UNIX system. Here we only list different section: -c Dir changes to the specified directory DIR before reading Makefile. -I DIR When you contain other makefile files, you specify a search directory using this option. -H Help text, display all Make options. -w The working directory is displayed before and after processing makefile. You can specify the goal to be compiled by the Target in the command line parameters, and allows simultaneously Rightening to compile multiple targets, compile the target files specified in the target option according to the order from left to right. If you do not specify a target in the command line, the system default target points to the first target file in the description file. Typically, Makefile also defines a Clean target, which can be used to clear the middle text during the compilation process. Parts, for example: Clean: RM -F * .O When running make clean, the RM -F * .O command will be executed, and finally delete all the intermediate files generated during all compilation processes. Implied rules In the Make tool contains some built-in or implicit rules, these rules define how never The same dependency file establishes a specific type of goal. UNIX systems typically support a file extension-based file name The implicit rules of the suffix. This suffix rule defines how to put a file with a specific file name suffix (for example, .c text) Parts), converted to files with another file name suffix (for example, .o file): .c: .o $ (Cc) $ (cflags) $ (cppflags) -c-@ @ $ < The default common file extension in the system and its meaning are: Target file .c C source file .f Fortran Source File .S assembly source file .y yacc-c source syntax .l lex source syntax YACC-C source syntax and LEX source syntax are also supported in the early UNIX system system. In the compilation process In the system, you will first look for .c files related to the target file in the Makefile file, if there is also related The .y and .l file, first convert it to the .C file, compile generation to generate the corresponding .o file; if there is no target Related .C files are only related .y files, the system will be directly compiled .y file. And GNU Make supports another type of implicit rules in addition to support suffix rules - mode rules then. This rule is more common because it can be used to define a more complex dependency rules using the mode rule. Pattern rule It looks very similar to the regular rules, but there are more than one% in front of the target name, and it can be used to define the purpose. The relationship between the standard and dependent files, such as the following mode rules define how to turn any file.c file Change to File.o file: % .c:%. O $ (Cc) $ (cflags) $ (cppflags) -c-@ @ $ < # EXample # A more comprehensive example will be given to the Makefile file and the Make command. One step, where the make command not only involves the C source file also includes YACC syntax. This example is selected from "UNIX Programmer's Manual 7th Edition, Volume 2a "Page 283-284 Here is the specific content of the description file: -------------------------------------------------- ------- #Description File for the make command #Send to print P = UND -3 | OPR -R2 #The Source Files That Are Need by Object Files FILES = Makefile Version.c defs main.c donamc.c Misc.c file.c / DOSYS.C gram.y lex.c gcos.c #The Definitions of Object Files Objects = vesion.o main.o donamc.o misc.o file.o dosys.o gram.o Libes = -ls LINT = Lnit -P Cflags = -o Make: $ (Objects) CC $ (CFLAGS) $ (Objects) $ (Libes) -o Make Size make $ (Objects): DEFS Gram.o: lex.c Cleanup: -rm * .o gram.c INSTALL: @Size Make / USR / BIN / MAKE CP Make / USR / BIN / MAKE; RM Make #Print Recently Changed FilesPrint: $ (files) PR $? | $ P Touch Print Test: Make -DP | Grep -V Time> 1zap / usr / bin / make -dp | grep -v Time> 2zap DIFF 1ZAP 2ZAP RM 1ZAP 2zap LINT: DOSYS.C DONAMC.C file.c main.c misc.c version.c gram.c $ (Lint) dosys.c donamc.c file.c main.c misc.c version.c / Gram.c RM gram.c Arch: Ar UV /SYS/SOURCE/S2/make.a $ (files) -------------------------------------------------- ------------ It is usually as defined above the description file to be as required to output the command to be executed. In executing After the MAKE command, the output result is: $ Make CC -C Version.c cc -c main.c CC-C Donamc.c CC-C Misc.c CC-C file.c CC-C DOSYS.C Yacc gram.y MV Y. Tab.c gram.c CC-C Gram.c CC Version.o main.o donamc.o misc.o file.o dosys.o gram.o / -Ls -o make 13188 3348 3044 = 19580B = 046174B The last digital information is the output result of the "@Size Make" command. The reason why only output results There is no corresponding command line, because the "@Size make" command starts with "@", this symbol is prohibited from printing it. The command line is located. The last few command lines in the description file are very useful in maintaining compiling information. "Print" The function line's role is that the printout is executed for all the changed file names after the last "make Print" command. system Using a 0-byte file named Print to determine the specific time to execute the print command, and the macro $? Then point to that Some file names of files that modified after the Print file change. If you want to specify the print command, Send the output result into a specified file, then modify the macro definition of P: Make Print "P = CAT> ZAP" Most software in Linux provide source code, rather than ready-made executables, this is Ask the user to configure it according to the actual situation of its own system, after compiling the source, the software can be used. Only by mastering the Make tool can let us really enjoy the belonging to Linux. Poor fun.
