How the ARM processor handles exception
When an exception occurs, the ARM processor completes the current command (except for the reset exception) as much as possible. And execute the following action:
1. Enter the operating mode corresponding to specific abnormalities.
2. Save the address of the next instruction caused by an exception command to the R14 of the new mode.
3. Save the original value of the CPSR to the new mode SPSR.
4. Disable IRQ by setting the 7th bit of CPSR. If an exception is fast interrupt. Then set up the 6th bit of the CPSR to disable fast interrupts.
5. Force the PC to assign the vector address value.
