General Description of Seven Flash Memory
The Flash of P89C669 has an erasable programmable function. Flash can read and write by byte, and the erase operation of the chip will delete all content, and block erasure can erase operations on the byte block of the memory. The programming and parallel programming within the system are valid. The on-chip erasing timing provides users with a friendly interface. P89C669 supports 10,000 effective erasing. The memory cell uses optimized erasing and programming technology to provide reliable multiplex processing using more advanced channel oxidation treatment techniques and low voltage erasing operations. P89C669 can be used as long as the 5V voltage is provided.
7.1 System programmable and field programmable features
1. Flash internal program support block erase
2. Internal 4k bytes of Boot Flash contains a low-level programming program and the default UART loader. Users can call to implement field programming IAP, or close Boot Flash to access 8M external extension space.
3. Boot vector allows users to put the program code to any place of Flash, greatly improve the flexibility of the application.
4. The default Boot Flash load is programmable through the UART0 interface, and does not require the user to provide a loader.
5. If the internal program store is forbidden to use EA = 0, then 8M external memory can be used.
6. 5V voltage can be erased
7. Byte Programming (20US)
8. Block (8K) erase time is <1 second, the entire Flash96K erase is <1 second
9. Implement parallel programming with programmatic connections using the interface of 87C51
10. Each byte supports 10,000 erase at least
11. Data can be stored at least 10 years
7.2 P87C51 processor processing capability based on Flash
7.2 .1 memory allocation
The P89C669 contains 96K bytes of Flash (MX universal sector range: 80: 0000-81: 7FFFH) and 2k bytes of in-chip.
Figure75
7.2.2Flash programmable erasure
There are three ways to erase Flash, and the first method provides an end user with a public entry point using a low-level programming program through Bootflash. End users must execute code using space outside the block being erased. The ISP Boot Loader of the second piece of UART0 is activated, and the end user can apply by calling the low-level programming program through the public entry point of Boot Flash. Third point erasing can use these devices using commercially available EPROM programs, parallel programming can be used similar to EPROM 87C51, but this is illegal, and existing commercial software must support these devices.
7.2.3 Boot Flash
When the microprocessor writes its own Flash memory, all low-level details are handled by the code called bootflash's 4KB memory by flash. The user program can complete the required operation as long as the corresponding public entry point is called. Bootflash processing includes some things: block erase, byte programming, check bytes, write secure lock bits, and more. Bootfalsh overlay address from 00: F000H to 00: fffh carried out.
: Note: In order to use bootflash, use the LCALL / CALL directive to call 00: F000H address, of course, RET is used to return it. In addition, this fixed call BootFlash's entry address can be placed in a 64K memory mapping table.
Figure 75
7.2.4 power-on execution of reset code
P89C669 has two special flash elements, one is a BootVector one is a status byte, and bootvector is a 16-bit register consisting of high BVH and an intermediate bvm. After generating the reset falling edge, the P89C669 detects the content of all status bytes. If the status byte content is 0, then the program starts to start executing at 00: 0000H, which is the initial start of the usual user application address. If the status byte is not 0, the address will be composed of BVH BVM (FCH) A7-0 (0), corresponding to 00: FC00H address boot flash isp boot loader execution. User Boot Loader can set up user bootloader by bootvector.
Note: When erase the Bootvector and status, these three bytes are erased simultaneously, and the user is necessary to rewrite the bootvector after erasing and renew the status bit.
7.3 Hardware activation Boot Loader
BootLoader can also perform Psen Low, EA> ViH (such as 5V) and Ale High when reset in the falling edge, which effects on setting status bytes. If the vendor starts the bootvector vector not 00: FC00h, it will not be loaded with the Bootflash pointing to the ISP. If so, only the contents of the BootVector are changed by parallel programming, which is not provided to the end user to apply an erased and programming BootVector and status bytes. After the brush is written, the status byte needs to be cleared and bootvector needs to set up to ensure that the client starts from 00: 0000h user start addresses next time.
7.4ISP
ISP does not need to perform operations by microcontrollers of mobile systems, and ISP is simple to be more convenient to program the P89C669 through a series of internal hardware resources and firmware combine. This firmware is provided by phiph and inlaid in the middle of each 669 device. Philip's ISP tool uses circuit embedded programming to increase the cost of devices and boards as small as possible. ISP features require 5 pins: TXD0, DXD0, VSS, VCC, VPP (Figure 76), which requires a connector to connect applications and external circuits to use these features. VPP provides appropriate weakening and VPP does not allow execution of data table restrictions. 7.4.1 Using ISP
Using UART0 for ISP systems to provide users with some features, using special definition protocols in the feature to perform and call through UART0. Most PCs are compatible with computing opportunities to send data through the serial port and then wait for the microcontroller to answer.
7.4.2IAP method
Some IAP uses the application to erase or rewrite the Flash section, all calls use a common interface, PGM_MTP, select the programmable function to select the programmable function before calling 00: FFF0 address PGM_MTP by setting the microprocessor register, the result is returned to the register. IAP call is represented in Table 25
7.4.3 Using WDT
