I need this time for this time. I have learned it before. I haven't used it for a long time. I have forgotten it (now getting more and more discovered that I can't remember things. It seems that it is no longer pure.). I have to take a look at the book, and I will sum up. First, the 8086, 8088 is a 16-bit processor, and after 80386 is a 32-bit processor, 80286 is a 16-bit processor, but has started from "real mode" to "protection in addressing mode. Mode "transition. BTW, when we say that a CPU is 16-bit or 32 bits, refers to the width of the ALU (calculation logic unit) in the processor. In the 8086, the width of the data bus is 16 bits (usually as Alu), the address bus is 20 bits, and the addressing space is 1m. Therefore, the segmentation method is used in 8086 to map 16-bit addresses to a 20-bit physical address. The 16-bit segment register corresponds to the high 16-bit of the address bus, and the segment address is left and then the 16-bit address in the interview command is formed, and the real 20-bit physical address is formed. However, under this mechanism, a "base address" is determined by the segment register, and one process can always access the 64K byte of the 64K byte since this started, and cannot be restricted. Further, by changing the contents of the segment register, this process can access any of the units in memory as you want, so I will not protect the protection of the system and other processes. This is the biggest shortcoming of "real mode". The 80286 of the transition does not talk. Starting from 80386, entered the real "protection mode". 386 is 32-bit CPUs, data, and address bits are 32 bits, so the addressing space is 4G. There are two ways to manage memory in 80386, one is segment memory management, one is a page-oriented memory management. Start from segment memory management first. Since Intel is based on a 16-bit CPU involving 32-bit CPUs, in the 32-bit processor, it inherits the segment register. Due to the increase in addressing space, the 16-bit segment register is unable to provide the base address. This introduces a data structure to describe some information about the segment (ie, the descriptor). When an interview instruction issues a memory address, the CPU implements the conversion of 32-bit logical addresses from the instructions in accordance with the following procedure: 1. First, which segment register is used according to the nature of the instruction. 2. According to the contents of the segment register, find the corresponding "segment description structure". 3. A base address is obtained from the "Segment Description Structure". 4. Use the address in the instruction as a displacement, see if it is downline than the segment length specified in the segment description; 5. Determine whether or not it is equivalent to the nature of the instruction and the access authority in the segment descriptor; 6. Finally The address in the instruction is added as a displacement, and the physical address is added to the segment base address. At the same time, in the above process, the protection is achieved due to the check of access rights. The "Segment Description Structure" mentioned above is actually the segment descriptor. There are two registers in 80386, respectively, of the global segment description table register (GDTR) and a partial segment description table register (LDTR) to point to a certain segment description table stored in memory. The high 13 bits in the original register indicate that a segment descriptor is offset in the segment description table, which is the address of the segment descriptor, which is obtained by adding the base address of the gdtr (or LDTR). Finally, the 32-bit base address and length of the segment is obtained from the segment description subsequent, and some information (this information includes about the offshore and permission check). Segment-type memory management is only a portion of the 386 protection mode, and the page memory management is developed due to its efficiency and the length of the problem. There is a register CR0 in the 386 processor. If its PG bit is 1, the page memory management is turned on.
