I. What is MMU, MMU's role MMU is an abbreviation for Memory Management Unit. For a variety of CPUs, MMU is an optional accessory. The MMU is responsible for the virtual address. The physical address of the physical address. Provide a memory access authorization for the hardware mechanism. Modern multi-user multi-process operating system, requires MMU to reach each user process to have its own independent address space target. Use MMU, OS to divide a address area, in this address area, every process The content is not necessarily the same. For example, the Microsoft Windows operating system is divided into user address space at address 4M-2G. Process A maps executable files in address 0x400000. Process B also maps executable files at address 0x400000. If A The process read address 0x400000, read is the content of A. The executable of the process B reads the address 0x400000, and the executable of B is read to the RAM. This is MMU The role of address translation. The 80386CPU or updated CPU is integrated in the 80386CPU or updated CPU. You can provide 32Bit total 4G address space. III. ARM series MMU ARM CPU, MMU as a coloration The processor exists. There is a different match according to different series. You need to query Datasheet to know if there is MMU. If there is, it must be a coprocessor numbered 15. You can provide 32Bit total address space. IV x86 launch MMU The post-addressed mode 1. The X86 MMU is provided with 4K / 2M / 4M Page mode (providing different capabilities according to different CPUs), which provides a description of the 4K Page mode currently used in most OS. And no part of Access Check. (After all, it is not a complete CPU manual.?) 2. Register A) GDTB) LDTC) CR0D) CR3E) Segment Register3. Virtual Address to the Physical Address Conversion Steps (Intel 2M / 4M The PAGE may be described in the future article) a) Segment Register as the GDT or LDEx of Index, take out the corresponding GDT / LDT Entry. Note: Segment is unable to cancel, even in flat mode. Saying Flat mode Using segment register is wrong. There are default s in any RAM addressing instruction. .. EGMENT unless SEGMENT OVERRIDE PREFIX is assumed to change the current address of the instruction SEGMENT, otherwise the format is the DEFAULT SEGMENT.i ENTRY typedef struct {UINT16 limit_0_15; UINT16 base_0_15; UINT8 base_16_23; UINT8 accessed: 1; UINT8 readable: 1; Uint8 cogn_data: 1; uint8 app_system: 1; uint8 dpl: 2; uint8 present: 1; uint8 limit_16_19: 4; uint8 unused: 1; uint8 always_0: 1; uint8 seg_16_32: 1; uint8 granularity: 1; UINT8 BASE_24_31;} code_seg_descriptor, * pcode_seg_descriptor; typedef struct {uint16 limit_0_15; uint16 base_0_15; uint8 base_16_23;
UINT8 ACCESSED: 1; uint8 expanddown: 1; uint8 code_data: 1; uint8 app_system: 1; uint8 dpl: 2; uint8 present: 1; uint8 limited: 1; uint8 unused: 1; uint8 always_0: 1; UINT8 seg_16_32: 1; UINT8 granularity: 1; UINT8 base_24_31;} DATA_SEG_DESCRIPTOR, * PDATA_SEG_DESCRIPTOR; ENTRY There are four formats, provided herein is a CODE SEGMENT DATA SEGMENT ENTRY and ENTRY in FLAT mode format as base_0_15, base_16_23 place. 0, and limit_0_15, limit_16_19 is at 0xfffff. granularity of the table 1. SEGMENT address space is removed from SEGMENT BASE aDDRESS LIMIT and at from 0 to 0XFFFFFFFF 4G address space .b). aDDRESS to be accessed is first aCCESS CHECK Whether it exceeds the restrictions of segment. C) The Address base address that will be accessed, forms a virtual address that requires 32bit access. This address is interpreted as the following format: typedef struct {uint32 offset: 12; uint32 PDBR_Index: 10; uint32 PDBR_INDEX: 10 } Va, * lpva; d) PDBR_INDEX As the CR3 INDEX, get a data structure TypedEf struct {uint8 present {uint8 present : 1; Uint8 Writable: 1; Uint8 Writty: 1; uint8 cachedisable: 1; uint8 accessed: 1; uint8 reserved1: 1; uint8 PageSIze: 1; uint8 ignoreed: 1; uint8 avl: 3; uint8 ptadr_12_15 : 4; UINT16 PTADR_16_31;} PDE, * LPPDE; E) Remove the address of the Page Table. And use Page_index as INDEX to get the following data structure typef struct {uint8 present: 1; uint8 Writable: 1; uint8 supervisor: 1; uint8 WriteTHROUGH: 1; UINT8 CACHEDISABLE: 1; UINT8 DIRTY: 1; UINT8 PTA: 1; UINT8 GLOBAL: 1; UINT8 AVL: 3; UINT8 PTADR_12_15: 4;
