CPU information

Recently, a CPU's information should be organized, it should be more comprehensive. Almost now all X86 CPUs have built-in CPUID instructions to distinguish between authenticity, some CPU vendors such as AMD, VIA, etc. also have built-in multi-extension CPUID instructions, which is more convenient. Below we use Delphi to implement a CPU detection software. The CPUID is as follows: ASM PUSH EAX PUSH EBX PUSH ECX PUSH EDX MOV EAX, X // **************************************** ************************* / / CPUID instruction, because Delphi's assembly compiler does not have built-in instructions, // So use the instrument language of the instruction Code $ 0f, $ A2 to implement // ************************************************ ************** DB $ 0F, $ A2 Pop EDX POP ECX POP EBX POP END; the parameter of the CPUID instruction is Eax, Mov Eax, X this sentence is to assign X to Eax. The returned parameters are stored in EAX, EBX, ECX, and EDX. We can write a function: type tcpuidResult = Record Eax: DWORD; EBX: DWORD; ECX: DWORD; EDX: DWORD; END; ... Function CPUID (EAX: DWORD): TCPUIDRESULT; ASM PUSH EDX PUSH EBX PUSH ECX PUSH EDX MOV Eax, eax // ***************************************************** ********* // CPUID instruction, because Delphi's assembly compiler does not have built-in instructions, // So use the machine language code of this instruction $ 0F, $ A2 to implement // ******* ******************************************************** DB $ 0 F, $ A2 Mov Result.eax, EAX Mov Result.ebx, Ebx Mov Result.ecx, ECX Mov Result.edX, EDX POP EDX POP ECX POP EBX POP EAXEND

CPUID parameter and return value list: eax = 0000_0000h Enter EAX = 0000_0000h gets the maximum value of the CPUID instruction and the manufacturer's name string output EAX = XXXX_XXXX to get the maximum value supported by the CPUID instruction # 1 EBX-EDX-ECX manufacturer's name string # 2 GenuineIntel Intel processor UMC UMC UMC UMC processor AuthenticAMD AMD processors CyrixInstead Cyrix processor NexGenDriven NexGen processor CentaurHauls Centaur processor RiseRiseRise Rise Technology processor GenuineTMx86 Transmeta processor Geode by NSC National Semiconductor DESCRIPTION processor # 1 Pre-B0 Step Intel P5 processor returns EAX = 0000_05xxh. # 2 pre-b0 STEP INTEL P5 processor can not return to the vendor string EAX = 0000_0001H Enter EAX = 0000_0001H Get the processor TYPE / FAMILY / MODEL / STEPPING and the appearance identifier Output EAX =

XXXX_XXXXH processor Type / Family / Model / Stepping Extended Family Extended Family is BITS 27..20. 00h Intel P4 01H Intel Itanium 2 (IA-64) Extended Model Extended Model is BITS 19..16. Type Type is Bit 13 and BIT 12. 11B Reserved 10B Second Block Processor 01b Overdrive Processor 00B First Processor Family Family is BITS 11..8. 4 MOST 80486SAMD 5x86Cyrix 5x86 5 Intel P5, P54C, P55C, P24TNEXGEN NX586CYRIX M1AMD K5, K6Centaur C6, C2, C3RISE MP6TRANSMETA CRUSOE TM3X00 and TM5X00 6 Intel P6, P2, P3AMD K7CYRIX M2, VIA CYRIX III 7 Intel Itanium (IA-64) f If this value is, see Extended Family Model Model is BITS 7..4. Intel F If yes, then this value depends on extended model Intel 80486 0 i80486DX-25/33 1 i80486DX-50 2 i80486SX 3 i80486DX2 4 i80486SL 5 i80486SX2 7 i80486DX2WB 8 i80486DX4 9 i80486DX4WB UMC 80486 1 U5D 2 U5S AMD 80486 3 80486DX2 7 80486DX2WB 8 80486DX4 9 80486DX4WB E 5x86 f 5x8 6WB Cyrix 5x86 9 5x86 Cyrix Mediagx 4 GX, GXM Intel P5-Core 0 P5 A-STEP 1 P5 2 P54C 3 P24T OverDrive 4 P55C 7 P54C 8 P55C (0.25μm) NexGen NX586 0 NX586 OR NX586FPU (Only Later Ones) Cyrix M1 2 6X86 Cyrix M2 0 6x86mx Via Cyrix III 5 Cyrix M2 Core 6 Winchip C5A Core 7 Winchip C5B Core (if Stepping = 0..7) 7 Winchip C5C Core (if Stepping = 8..f) 8 Winchip C5C-T Core IF stepping = 0..7) AMD K5 0 SSA5 (Pr75, Pr90, Pr100) 1 5k86 (Pr120, Pr133) 2 5k86 (PR166) 3 5 k86 (PR200) ​​AMD K6 6 k6 (0.30 μm) 7 k6 (0.25 μm) 8 K6-2 9 K6-III D K6-2 OR K6-III

(0.18 μM) CENTAUR 4 C6 8 C2 9 C3 Rise 0 MP6 (0.25 μm) 2 MP6 (0.18 μm) Transmeta 4 CrusoE TM3X00 and TM5X00 Intel P6-Core 0 P6 A-Step 1 P6 3 P2 (0.28 μm) 5 p2 ( 0.25 μM) 6 p2 WITH ON-DIE L2 Cache 7 P3 (0.25 μm) 8 p3 (0.18 μm) with 256 KB ON-DIE L2 Cache A P3 (0.18 μm) with 1 or 2 MB ON-DIE L2 Cache B P3 ( 0.13 μM) with 256 or 512 KB ON-DIE L2 Cache AMD K7 1 Athlon (0.25 μM) 2 Athlon (0.18 μm) 3 DURON (SF Core) 4 Athlon (TB Core) 6 Athlon (PM Core) 7 DURON (Mg Core) 8 Athlon (TH Core) A athlon (Barton Core) Intel P4-Core 0 P4 (0.18 μM) 1 P4 (0.18 μM) 2 P4 (0.13 μm) 3 p4 (0.09 μm) Stepping Stepping at BITS 3..0. Stepping describes the details of the processor. Ebx = aall_ccbh brand ID Brand ID is 7..0. 00h does not support 01h 0.18 μm Intel Celeron 02H 0.18 μM Intel Pentium III 03H 0.18 μM Intel Pentium III Xeon 03H 0.13 μ m Intel Celeron 04h 0.13 μm Intel Pentium III 07h 0.13 μm Intel Celeron mobile 06h 0.13 μm Intel Pentium III mobile 0Ah 0.18 μm Intel Celeron 4 08h 0.18 μm Intel Pentium 4 09h 0.13 μm Intel Pentium 4 0Eh 0.18 μm Intel Pentium 4 Xeon 0Bh 0.18 μm Intel Pentium 4 Xeon MP 0Bh 0.13 μm Intel Pentium 4 Xeon 0Ch 0.13 μm Intel Pentium 4 Xeon MP 08h 0.13 μm Intel Celeron 4 mobile 0Eh 0.13 μm Intel Pentium 4 mobile (production) 0Fh 0.13 μm Intel Pentium 4 mobile (samples) CLFLUSH CLFLUSH ( 8-byte) in BITS 15..8. CPU Count logic processor quantity bits 23..16. APIC ID default (fixed) APIC ID is BITS 31..24. ECX =

XXXX_XXXXH Feature Flags Description Bits 31 ... 11 Reserved Bit 10 (CID) Context ID: L1 data cache can be set to adapt or shared mode BIT 9 Reserved Bit 8 (TM2) calories 2 BIT 7 Reserved Bit 6 Reserved Bit 5 Reservation Bit 4 (DSCPL) CPL-Qualified Debug Store Bit 3 (MON) Monitor Bit 2 Reserved Bit 1 Reserved Bit 0 (SSE3) SSE3, MXCSR, Cr4.OSxmmexcpt, #xf, if FPU = 1 also supports fisttp edx = xxxx_xxxx bit 31 (PBE) Pending Break Event, STPCLK, FERR #, MISC_ENABLE MSR bit 30 (IA-64) IA-64 bit 29? THERM_INTERRUPT, THERM_STATUS, and MISC_ENABLE MSRsxAPIC thermal LVT entry bit 28 (HTT) Hyper-Threading Technology bit 27 (SS) SelfSnoop Bit 26 (SSE2) SSE2, MXCSR, Cr4.OSxmmexcpt, #xf Bit 25 (SSE) SSE, MXCSR, Cr4.OSXMMEXCPT, #xf bit 24 (fxsr) FXSAVE / FXRSTOR, CR4.OSFXSR bit 23 (MMX ) Mmx bit 22 (ACPI) Therm_control MSR Bit 21 (DTES) Debug TRACE AND EMON Store MSRS Bit 20 Reserved Bit 19 (CLFL) CLFLUSH BIT 18 (PSN) PSN (See Standard Eax = L 0000_0003H), PSN_Disable MSR # 1 bit 17 (PSE36) 4 MB PDE BITS 16..13, CR4.PSE BI T 16 (PAT) PAT MSR, PDE / PTE.PAT Bit 15 (CMOV) CMOVCC, IF FPU = 1 THEN ALSO FCMOVCC / F (U) COMI (P) Bit 14 (MCA) MCG _ * / MCN_ * MSRS, CR4. MCE, #MC Bit 13 (PGE) PDE / PTE.G, Cr4.pge Bit 12 (mtrr) mtrr * MSRS bit 11 (SEP) SYSENTER / SYSEXIT, SESETER / SYSEXIT, SEP_ * MSRS # 2 Bit 10 Reserved Bit 9 (APIC) APIC # 3, # 4 bit 8 (CX8) CMPXCHG8B # 5 Bit 7 (MCE) MCAR / MCTR MSRS, CR4.MCE, #MC Bit 6 (PAE) 64bit PDPTE / PDE / PTES, CR4.PAE Bit 5 (MSR) MSRS, RDMSR / WRMSR Bit 4 (TSC) TSC, RDTSC, CR4.TSD (Doesn't Imply MSR = 1) Bit 3 (PSE) PDE.ps, PDE / PTE.RES, CR4.PSE, #PF (1xxxb) Bit 2 (De) cr4.de, dr7.rw =

10b, #ud on mov from / to DR4 / 5 Bit 1 (VME) CR4.VME / PVI, EFLAGS.VIP/VIF, TSS32.IRB bit 0 (FPU) FPU Description # 1 If the PSN invalid PSN appearance is 0 Although the Intel P6 processor does not support SEP, it is still false here (I really don't know what Intel thinks). # 3 APIC is invalid, then the APIC looks sign is 0. # 4 early AMD K5 processor (SSA5) Support PGE. # 5 processor does support CMPXCHG8B but the default is the report is not supported. In fact, this is a bug.eax = 0000_0002H input EAX = 0000_0002H for Windows NT to obtain the processor configuration Description Output EAX.15..8EAX.23. . 16EAX.31..24ebx.0..7ebx.15..8ebx.23..16ebx.31..24ecx.0..7ecx.15..8ecx.23..16ecx.31..24edx.0. .7edx.15..8edx.23..16edx.31..24 Configuration Description Note 00h Null Descriptor (= unused descriptor) 01H Code TLB, 4K Pages, 4 Ways, 32 Entries 02H Code TLB, 4M Pages, Fully, 2 Entries 03H Data TLB, 4K Pages, 4 Ways, 64 Entries 04h Data TLB, 4M Pages, 4 Ways, 8 Entries 06H Code L1 Cache, 8 KB, 4 WAYS, 32 BYTE LINES 08H Code L1 Cache, 16 KB, 4 Ways , 32 Byte Lines 0ah Data L1 Cache, 8 KB, 2 Ways, 32 Byte Lines 0ch Data L1 Cache, 16 KB, 4 Ways, 32 Byte Lines 10h Data L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES (IA-64 15 H Code L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES (IA-64) 1AH Code and Data L2 Cache, 96 KB, 6 WAYS, 64 BYTE LINES (IA-64) 22H Code and Data L3 Cache, 512 KB, 4 Ways (!

), 64 byte lines, dual-sectored 23h Code And Data L3 Cache, 1024 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED 25H Code And Data L3 Cache, 2048 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED 29H Code and Data L3 Cache, 4096 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED 39H Code And Data L2 Cache, 128 KB, 4 WAYS, 64 BYTE LINES, SECTORED 3BH CODE AND DATA L2 Cache, 128 KB, 2 WAYS, 64 Byte Lines, Sectored 3ch Code and Data L2 Cache, 256 KB, 4 Ways, 64 Byte Lines, Sectored 40h No Integrated L2 Cache (P6 Core) OR L3 Cache (P4 Core) 41H Code and Data L2 Cache, 128 KB, 4 Ways, 32 Byte Lines 42H Code and Data L2 Cache, 256 KB, 4 Ways, 32 Byte Lines 43h Code And Data L2 Cache, 512 KB, 4 WAYS, 32 BYTE LINES 44H Code And Data L2 Cache, 1024 KB, 4 WAYS, 32 Byte Lines 45H Code and Data L2 Cache, 2048 KB, 4 WAYS, 32 BYTE LINES 50H CODE TLB, 4K / 4M / 2M Pages, Fully, 64 Entries 51H Code TLB, 4K / 4M / 2M Pages, Fully, 128 Entries 52H Code TLB, 4K / 4M / 2M Pages, Fully, 256 Entries 5bh Data TLB, 4K / 4M Pages, Fully, 64 Entries 5ch Data TLB, 4K / 4M Pages, Fully, 128 Entries 5d Data TLB, 4K / 4M Pages, Fully, 256 Entries 66h Data L1 Cache, 8 KB, 4 WAYS, 64 Byte Lines, Sectored 67h Data L1 Cache, 16 KB, 4 WAYS, 64 BYTE LINES, SECTORED 68H DATA L1 Cache, 32 KB, 4 WAYS, 64 BYTE LINES, SECTORED 70H TRACE L1 Cache, 12 k μOps, 8 Ways 71h Trace L1 Cache, 16 K μOops, 8 Ways 72H TRACE L1 Cache, 32 K μOops, 8 Ways 77H Code L1 Cache, 16 KB, 4 WAYS, 64 BYTE LINES, SECTORED (IA-64) 79H Code and Data L2 Cache, 128 KB, 8 Ways , 64 Byte Lines, Dual-Sectored 7ah Code and Data L2 Cache, 256 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED 7BH CODE AND DATA L2 Cache, 512 KB, 8 WAYS, 64 BYTE LINES,

Dual-sectored 7ch Code and Data L2 Cache, 1024 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED 7EH CODE AND DATA L2 Cache, 256 KB, 8 WAYS, 128 BYTE LINES, "SECT. (IA-64) 81H Code And Data L2 Cache, 128 KB, 8 WAYS, 32 BYTE LINES 82H Code And Data L2 Cache, 256 KB, 8 Ways, 32 Byte Lines 83h Code And Data L2 Cache, 512 KB, 8 WAYS, 32 BYTE LINES 84H Code and Data L2 Cache, 1024 KB, 8 WAYS, 32 BYTE LINES 85H Code and Data L2 Cache, 2048 KB, 8 WAYS, 32 BYTE LINES 88H Code And Data L3 Cache, 2048 KB, 4 WAYS, 64 BYTE LINES (IA-64) 89H Code and Data L3 Cache, 4096 KB, 4 WAYS, 64 BYTE LINES (IA-64) 8AH Code and Data L3 Cache, 8192 KB, 4 WAYS, 64 BYTE LINES (IA-64) 8DH Code and Data L3 Cache, 3096 KB , 12 WAYS, 128 BYTE LINES (IA-64) 90H Code TLB, 4K ... 256M Pages, Fully, 64 Entries (IA-64) 96H Data L1 TLB, 4K ... 256M Pages, Fully, 32 Entries (IA-64) 9BH Data L2 TLB, 4K ... 256M Pages, Fully, 96 Entries (IA-64) Value Description 70H Cyrix Specific: Code and Data TLB, 4K Pages, 4 Ways, 32 Entries 74H Cyrix Specific: ??? 77h Cyrix Specific: ??? 80h Cyrix Specific: Code and Data L1 Cache, 16 KB, 4 WAYS, 16 BYTE LINES 82H CYRIX Specific: ??? 84h Cyrix Specific: ?? • Value Description Others reserves an example there is a P6 EAX = 0302_0101HEBX = 0000_0000hecx = 0000_0000HEDX = 0604_0A43H This P6 processor contains 4K / m code / data TLB,

8 8 KB Code / Data L1 Cache and Mixed 512 KB Code / Data L2 Cache. Description # 1 Special attention to the multiprocessor system, should be executed. EAX = 0000_0003H input EAX = 0000_0003H Get the processor serial number # 1 Output EBX = XXXX_XXXXH processor serial number (just transmeta crusoe) ECX = xxxx_xxxh processor serial number EDX = xxxxxxxh processor serial number Description # 1 When PSN is valid. EAX = 8000_0000h input EAX = 8000_0000h gets the extended CPUID instruction and the maximum support of the manufacturer name string output EAX = xxxx_xxxxh maximum EBX-EDX-ECX manufacturer name string AuthenticAMD AMD Cyrix reserved reserved reserved Centaur Intel TransmetaCPU Transmeta reserved National Semiconductor extended EAX = 8000_0001h processor to obtain input EAX = 8000_0001h family / model / stepping and features flags # 0 output EAX = 0000_0xxxh processor family / model / stepping family Family is bits 11..8. 5 AMD K5Centaur C2Transmeta Crusoe TM3x00 and TM5x00 6 AMD K6VIA Cyrix III 7 AMD K7 model model is bits 7..4. AMD K5 1 5k86 (Pr120 or Pr133) 2 5k86 (PR166) 3 5K86 (PR200) ​​AMD K6 6 K6 (0.30 μm) 7 k6 (0.25 μm) 8 K6-2 9 K6-III D K6-2 OR K6-III (0.18 μm) AMD K7 1 Athlon (0.25 μM 2 Athlon (0.18 μm) 3 DURON (sf core) 4 Athlon (TB Core) 6 Athlon (PM Core) 7 DURON (Mg Core) 8 Athlon (TH Core) A Athlon (Barton Core) Centaur 8 C2 9 C3 VIA CYRIX III 5 Cyrix M2 Core 6 Winchip C5a Core 7 Winchip C5B Core (if Stepping = 0..7) Winchip C5C Core (if Stepping = 8..f) 8 Winchip C5c-T Core (if Stepping = 0..7 ) Transmeta 4 Crusoe TM3x00 and TM5x00 stepping stepping is bits 3..0. Stepping value of the details of the processor. EDX = xxxx_xxxxh feature flags description of indicated feature bit 31 (3DNow!) 3DNow! bit 30 (3DNow! ) extended 3DNOW! BIT 29 (L

M) AA-64, Long Mode (that is, AMD x86-64 instruction set) Bit 28 Reserved BITS 27..25 Reserved Bit 24 (MMX ) Bit 24 (FXSR) Cyrix Specific: Extended MMXAMD K7: FXSave / Fxrstor, CR4 .OSFXSR bit 23 (MMX) MMX bit 22 (MMX ) AMD Specific: MMX-SSE AND SSE-MEM BIT 21 Reserved Bit 20 (NX) Efer.NXE, P? E.NX, #PF (1xxxx) Bit 19 (MP ) MP-CAPABLE # 3 Bit 18 Reserved Bit 17 (PSE36) 4 MB PDE BITS 16..13, Cr4.PSE Bit 16 (FCMOV) Bit 16 (PAT) FCMOVCC / F (U) COMI (P) (Implies FPU = 1) AMD K7: PAT MSR, PDE / PTE.PAT Bit 15 (CMOV) CMOVCC Bit 14 (MCA) MCG _ * / MCN_ * MSRS, CR4.MCE, #MC bit 13 (PGE) PDE / PTE.g, CR4. PGE Bit 12 (mtrr) mtrr * MSRS Bit 11 (SEP) Syscall / Sysret, Efer / Star MSRS # 1 Bit 10 Reserved # 1 bit 9 (apic) APIC # 2 Bit 8 (CX8) CMPXCHG8B BIT 7 (MCE) MCAR / MCTR MSRS, CR4.MCE, #MC Bit 6 (PAE) 64bit PDPTE / PDE / PTES, CR4.PAE Bit 5 (MSR) MSRS, RDMSR / WRMSR Bit 4 (TSC) TSC, RDTSC, CR4.TSD (Doesn't IMPLY MSR = 1) Bit 3 (PSE) PDE.ps, PDE / PTE.RES, CR4.PSE, #PF (1xxxxB) Bit 2 (DE) CR4.DE, DR7.RW = 10b, #ud O N MOV from / to DR4 / 5 Bit 1 (VME) CR4.VME / PVI, EFLAGS.VIP/VIF, TSS32.IRB Bit 0 (FPU) FPU Description # 0 Intel processor does not support; return value EAX, EBX, ECX, and EDX are 0. # 1 AMD K6 processor, Model 6, Uses uses the tenth directive Sep. # 2 If the APIC is invalid, the APIC is read 0. # 3 AMD CPUID = 0662H K7 If the processor may also report the generation of the multiprocessor capability, 0EAX = 8000_0002H, 8000_0003H, and 8000_0004h input EAX = 8000_0002H Get the first portion of the processor name EAX = 8000_0003H Get the second part of the processor name EAX = 8000_0004H to process Part 3 output EAXEBXECXEDX processor name string # 1 AMD K5 AMD-K5? Processor AMD K6 AMD-K6TM W / MULTIMEDIA EXTENSIONS AMD K6-2 AMD-K6? 3D processor AMD-K6? -2 processing AMD K6-III AMD-K6? 3D processor AMD-K6? -III processor AMD K6-2 AMD-K6? -III processor (?) AMD K6-III AMD-K6? -III processor (? ) AMD K7 AMD-K7? Processor (Model 1) AMD AT

HLON? Processor (Model 2) AMD Athlon? Processor (Models 3/4, 6/7, And 8 - Programmable) Centaur C2 # 2 IDT Winchip 2IDT Winchip 2-3D Via Cyrix III CYRIX III? (?) VIA Samuel (?) VIA EZRA (?) Intel P4 Intel? Pentium? 4 CPU XXXXMHZ (Right-Justified, Leading Whitespaces) By the way, Intel has only P4 or more support. TRANSMETA TRANSTA? CRUSOE? Processor TMXXXX Description Content # 1 is a character array, ending with 0H. # 2 Winchip supports decision to support 3D Now! . EAX = 8000_0005H Enter Eax = 8000_0005H Get L1 Cache Capacity and Entrance Quantity # 1 Output EAX 4/2 MB L1 Entry Information EAX Bits 31..24 Data TLB Associative (FFH = FULL) 23..16 Data TLB Entries 15 .. TLB Associative 7..0 Code TLB Entries ECX Data L1 Information Description Bits Description 31..24 Data L1 Cache Size In KBS 23..16 Data L1 Cache Associative (FFH = FULL) 15..8 Data L1 Cache Lines Per Tag 7..0 Data L1 Cache Line Size In BYtes Edx Code L1 Information Description Bits Description 31..24 Code L1 Cache Size In KBS 23..16 Code L1 Cache Associative (FFH = FULL) 15..8 CODE L1 Cache Lines Per Tag 7..0 Code L1 Cache Line Size In Bytes Description Description # 1 Cyrix processor Use 0000_0002H to do a similar description EAX = 8000_0006H input EAX = 8000_0006H Get L1 cache capacity and port number output EAX 4/2 MB L2 Entrance Information # 1 bit Description 31..28 Data TLB Associative # 27..16 Data TLB Entries 1 5..12 Code TLB Associative # 2 11..0 Code TLB Entries EBX 4 KB L2 entrance information bit describes 31..28 Data TLB Associative # 1 27..16 Data TLB Entries 15..12 Code TLB Associative # 1 11 ..0 Code TLB Entries ECX Unified L2 Cache Information # 32 Bits Description 31..16 # 4 Unified L2 Cache Size In KBS # 3 15.

.12 # 4 unified L2 Cache Associative # 1 11..8 # 4 unified L2 Cache Lines Per tag 7..0 unified L2 cache line size in bytes Description # 1 0000B = L2 OFF, 0001B = Direct Mapped, 0010B = 2 -way, 0100b = 4-WAY, 0110B = 8-WAY, 1000B = 16-WAY, 1111B = FULL # 2 AMD K7 processor L2 Cache must depend on this information. # 3 AMD PUID = 0630H K7 processor (DURON 2 has 64 kb level 2 caching, but report only 1kb. # 4 VIA Cyrix III CPUID = 0670..068FH (C5B / C5C) processor error report BITS 31..24, 23..16, and 15 .. 8.EAX 8000_0007h input EAX = 8000_0007h power management information (EPM) Description of the output EDX EPM flags reserved 31..3 2 (VID) voltage ID control supported 1 (FID) frequency ID control supported 0 temperature sensing diode supportedEAX = 8000_0008h input EAX = 8000_0008H Get Address Size Information Output EAX Address Size Information Description 31..16 Reserved 15..8 Virtual Address Bits 70 Physical Address BitStransmeta EAX = 8086_0000H Enter EAX = 8086_0000H Get the maximum support for CPUID and vendor string Output EAX = XXXX_XXXXH Maximum Support EAX = L EBX-EDX-ECX Vendor Strings TransmetA Processortransmeta Eax = 8086_0001H Input EAX = 8086_0001H Get Processor Information Output EAX = 0000_0xxxh Processor Information Family THE family is encoded in bits 11..8. 5 Transmeta Crusoe TM3x00 and TM5x00 model The model is encoded in bits 7..4. Transmeta 4 Crusoe TM3x00 and TM5x00 stepping The stepping is encoded in bits 3..0. The stepping values ​​are processor-specific EBX = aabb_ccddh hardware revision (ab-cd), if 2000_0000h:. see EAX = l 8086_0002h register EAX instead ECX = xxxx_xxxxh nominal core clock frequency (MHz) EDX = xxxx_xxxxh feature flags description of indicated feature bits 31..4 RESERVED BIT 3 (LRTI) Longrun Table Interface 2 (???) Unknown Bit 1 (LR) LONGRUN BIT 0 (BAD) Recovery CMS Active (Due to A Fai

led upgrade) Transmeta EAX = 8086_0002h input EAX = 8086_0002h processor outputs information obtained EAX xxxx_xxxxh reserved or hardware revision (xxxxxxxxh) see EAX = l 8086_0001h register EBX for details EBX aabb_ccddh software revision, part 1/2 (abc-dx) ECX xxxx_xxxxh Software Revision, Part 2/2 (ABC-DX) Transmeta EAX = 8086_0003H, 8086_0004H, 8086_0005H, AND 8086_0006H Input EAX = 8086_0003H Get Information String First Part Eax = 8086_0004H Get Information String First Part Eax = 8086_0005H Get Information String Part of EAX = 8086_0006H Get information string first part output EAX-EBX-ECX-EDX information string # 1 Transmeta 20000805 23:30 Official release 4.1.4 # 2 (example) Description # 1 String ending at 00h is. Transmeta EAX = 8086_0007H Input EAX = 8086_0007H Get Processor Information Output EAX XXXX_XXXXH Current Clock Frequency (MHz) EBX XXXX_XXXXH Current Voltage (MV) ECX XXXX_XXXXH Current Opportunity (0..100%) EDX XXXX_XXXXH Current Delay (FS) Mysterious function EAX = 8FFF_FFFEh input EAX = 8FFF_FFFEh unknown # 1 output EAX 0049_4544h DEI (according to one source: Divide Et Impera = Divide And Rule) EBX 0000_0000h reserved ECX 0000_0000h reserved EDX 0000_0000h reserved explanatory # 1 this method is only supported AMD K6. Mysterious function EAX = 8FFF_FFFFH input eax = 8FFF_FFFFh Unknown # 1 output EAXEBXECXEDX string NexGenerationAMD explanatory # 1 This method is only he AMD K6 support other input EAX = xxxx_xxxxh other output EAX = xxxx_xxxxhEBX = xxxx_xxxxhECX = xxxx_xxxxhEDX = xxxx_xxxxh ambiguous code is as follows:. Type TCPUIDResult = packed record EAX: Dword EBX: DWORD; ECX: DWORD; EDX: DWORD; End; TCPUINFO = Packed Record Name: String [48]; BRAND: WORD; APIC: DWORD; vendor: string [12]; frequency: real; family: integer; model : integer; Stepping: integer; Efamily: integer; Emodel: integer; Estepping: integer; MMX: Boolean; MMXPlus: Boolean; AMD3DNow: Boolean; AMD3DNowPlus: Boolean; SSE: Boolean; SSE2: Boolean; IA64: Boolean;

X86_64: Boolean; End; Function CPUID (EAX: DWORD): TCPUIDRESULT; VAR Reax, Rebx, Recx, REDX: DWORD; Begin ASM PUSH EAX PUSH EBX PUSH ECX PUSH EDX MOV EAX, EAX // ******* ******************************************************* / / CPUID Instructions, because Delphi's assembly compiler does not have built-in instructions, // So use the instrument language code of the instruction $ 0f, $ A2 to implement // ***************************** ********************************** DB $ 0F, $ A2 MOV Reax, EAX MOV Rebx, EBX MOV RECX, ECX MOV REDX, EDX POP ED; Result.eax: = Reax; Result.ebx: = Rebx; Result.ecx: = RECX; Result.edx: = REDX;

function GetCPUSpeed: Real; const timePeriod = 1000; var HighFreq, TestFreq, Count1, Count2: int64; TimeStart: integer; TimeStop: integer; ElapsedTime: dword; StartTicks: dword; EndTicks: dword; TotalTicks: dword; begin StartTicks: = 0 Endticks: = 0; if QueryperFormanceFrequency (highfreq) THEN BEGIN

Testfreq: = Highfreq Div 100;

QueryperformanceCounter (count1); Repeat QueryperFormanceCounter (count2); Until Count1 <> count2; ASM PUSH EBX XOR EAX, EAX XOR EBX, EBX XOR ECX, ECX XOR EDX, EDX DB $ 0F, $ A2 /// CPUID DB $ 0F, $ 31 /// RDTSC MOV StartTicks, EAX POP EBX END;

Repeat QueryperFormanceCounter (count1); Until Count1 - count2> = TestfReq;

ASM PUSH EBX XOR EAX, EAX XOR EBX, EBX XOR ECX, ECX XOR EDX, EDX DB $ 0F, $ A2 /// CPUID DB $ 0F, $ 31 /// RDTSC MOV ENDTICKS, EAX POP EBX END;

Elapsedtime: = MULDIV (count1 - count2, 1000000, highfreq); end else begin timebeginperiod (1); timestart: = TimegetTime

Repeat TimeStop: = TimegetTime; Until TimeStop <> TimeStart; ASM PUSH EBX XOR EAX, EAX XOR EBX, EBX XOR ECX, ECX XOR EDX, EDX DB $ 0F, $ A2 /// CPUID DB $ 0F, $ 31 /// RDTSC Mov StartTicks, EAX POP EBX END;

Repeat TimeStart: = TimegetTime; Until TimeStart - TimeStop> = TimePeriod;

ASM PUSH EBX XOR EAX, EAX XOR EBX, EBX XOR ECX, ECX XOR EDX, EDX DB $ 0F, $ A2 /// CPUID DB $ 0F, $ 31 /// RDTSC MOV ENDTICKS, EAX POP EBX END; TIMEENDPERIOD (1) ;

ELAPSEDTIME: = (TimeStart - TimeStop) * 1000; End; Totalticks: = endticks - startticks; result: = TOTALTICKS / ELAPSEDTIME; END;

Function getcpuinfo: tcpuinfo; type tregchar = array [0..3] of char; var lvcpuid: tcpuidresult; i: integer; begin lvcpuid: = cpuid (0); result.vendor: = Tregchar (lvcpuid.ebx) Tregchar ( Lvcpuid.edx) TregChar (LVCPUID.ecx); lvcpuid: = CPUID (1); Result.Frequency: = getcpuspeed; Result.Family: = (LVCPUID.EAX AND $ F00) SHR 8; Result.Model: = (LVCPUID . Acpuid.Eax and $ f); result.eax and $ 7800000) SHR 20; Result.Eax and $ 7800000) SHR 20; Result.emodel: = (lvcpuid.eax and $ 78000) SHR Result.estepping: = (lvcpuid.eax and $ f); result.apic: = (LVCPUID.EBX and $ 1FE00000) SHR 23; Result.brand: = LVCPUID.EBX and $ 7F; Result.mmx: = lvCPUID.EDX and $ 800000) = $ 800000; Result.SSE: = (lvCPUID.EDX and $ 2000000) = $ 2000000; Result.SSE2: = (lvCPUID.EDX and $ 4000000) = $ 4000000; Result.IA64: = (lvCPUID.EDX and $ 40000000 = $ 40000000; lvcpuid: = CPUID ($ 800000000); Result.mmxPlus: = (lvcpuid.edx and $ 800000) = $ 800000; Result.Amd3DNow: = (LVCPUID.EDX A nd $ 10000000) = $ 10000000; Result.AMD3DNowPlus: = (lvCPUID.EDX and $ 8000000) = $ 8000000; Result.X86_64: = (lvCPUID.EDX and $ 40000000) = $ 40000000; if (Result.Vendor = 'GenuineIntel') and ((Result .Family <> 15) or (Result.Efamily <> 0)) The result.name: = Result.vendor 'processor' else begin result.name: = '; for i: = 2 to 4 do begin lvcpuid: = CPUID ($ 80000000 i); Result.Name: = Result.Name Treg Char (LVCPUID.EAX) Tregchar (Lvcpuid.ebx) Tregchar (LVCPUID.ECX) Tregchar (LVCPUID.EDX);

End; Result.Name: = trim (result.name); end; end; procedure tform1.formshow (sender: TOBJECT);

Procedure Writesupport (ed: boolean); Begin if suphen Edit.text: = 'Support' else edit.text: = 'does not support'; end; var CPU: TCPUInfo; Begin CPU: = getcpuinfo; editcpuname. Text: = cpu.name; editvendor.text: = cpu.vendor; editf.text: = INTOSTR (CPU.FAMIL); Editm.Text: = INTOSTR (CPU.MODEL); Editstep.Text: = INTOSTR (CPU.STEpping Editfe.Text: = INTTOSTR (CPU.efamily); Editme.Text: = INTOSTOSTR (CPU.EMODEL); Editstepe.Text: = INTOSTR (CPU.ESTEPPING); Edit33.Text: = INTOSTR (CPU.APIC); Editbrand.Text: = INTTOSTR (CPU.BRAND); Editspeed.Text: = formatfloat ('###. ##', cpu.frequency); WriteSupport (Editmmx, CPU.mmx); WritSupport (Editsse, CPU.SSE) ; WriteSupport (EditSSE2, CPU.SSE2); WriteSupport (EditIA64, CPU.IA64); WriteSupport (EditMMXp, CPU.MMXPlus); WriteSupport (Edit3DNow, CPU.AMD3DNow); WriteSupport (Edit3DNowp, CPU.AMD3DNowPlus); WriteSupport (EditX86_64, CPU.X86_64); END;

A true CPU detection software is also able to detect cache information, and the like. You can refer to the parameters shown in the table below, and extend in these code.

The information of the CPU is so hard to find. Intel and AMD are still better, and other companies are simply a large sea. I tried my best, I can only sort out.