CPU Support Code

#ifndef CPU_SUPPORT_H # define CPU_SUPPORT_H #define CPU_SUPPORTS_CPUID (0x00000001L) #define CPU_SUPPORTS_FPU (0x00000002L) #define CPU_SUPPORTS_MMX (0x00000004L) #define CPU_SUPPORTS_INTEGER_SSE (0x00000008L) #define CPU_SUPPORTS_SSE (0x00000010L) #define CPU_SUPPORTS_SSE2 (0x00000020L) #define CPU_SUPPORTS_3DNOW (0x00000040L) #define CPU_SUPPORTS_3DNOW_EXT (0x00000080L) long cpugetsupportedextensions (); #ENDIF --------------------------------------- -------------------------------------------------- --------------------- # include #include #include "cpusupport.h" static long g_lcpueXtensionsavailable; // this is ridiculous ??? static long CPUCheckForSSESupport () {__try {// __asm ​​andps xmm0, xmm0 __asm ​​_emit 0x0f __asm ​​_emit 0x54 __asm ​​_emit 0xc0} __except (EXCEPTION_EXECUTE_HANDLER) {// The operating system does not recognize andps. Reset them. if (_exception_code () == status_illegal_instruction ) G_lCPUExtensionsAvailable & = ~ (CPU_SUPPORTS_SSE | CPU_SUPPORTS_SSE2);} return g_lCPUExtensionsAvailable;} long __declspec (naked) CPUGetSupportedExtensions () {__asm ​​{push ebp push edi push esi push ebx xor ebp, ebp; cpu flags - if we do not have CPUID We probably; WON't want to try fpu optimizations. Pushfd; Flags -> Eax Pop Eax or Eax, 00200000H; Set The ID Bit Push Eax; Eax -> Flags Popfd Pushfd; Flags -> EAX POP Eax and Eax, 00200000H; ID Bit Set? JZ Done; Nope ...; CPUID EXISTS, Check for Features Register. Mov EBP, 00000003H XOR EAX, EAX CPUID OR EAX, EAX JZ DONE; No Features Register ?!?;

Features Register EXISTS, LOOK for MMX, SSE, SSE2. MOV EAX, 1 CPUID MOV EBX, EDX AND EBX, 00800000H; MMX IS Bit 23 SHR EBX, 21 or EBP, EBX; SET BIT 2 IF MMX EXISTS MOV EBX, EDX AND EDX, 02000000H; SSE IS BIT 25 SHR EDX, 25 NEG EDX AND EDX, 00000018H; SET BITS 3 and 4 if SSE EXISTS or EBP, EDX AND EBX, 04000000H; SSE2 IS Bit 26 SHR EBX, 21 and EBX, 00000020H; SET bit 5 or ebp, ebx; check for vendor feature register (K6 / Athlon) mov eax, 80000000h cpuid mov ecx, 80000001h cmp eax, ecx jb done;. vendor feature register exists, look for 3DNow and Athlon extensions mov eax, ecx! CPUID MOV EAX, EDX AND EDX, 80000000H; 3DNOW! IS Bit 31 SHR EDX, 25 or EBP, EDX; SET BIT 6 MOV EDX, EAX and Eax, 40000000H; 3DNOW! 2 IS Bit 30 SHR EAX, 23 or EBP, EBP, EBP SET BIT 7 and EDX, 00400000H; AMD MMX Extensions (Integer SSE) IS Bit 22 SHR EDX, 19 or EBP, EDX DONE: MOV EAX, EBP MOV G_LCPUEXTENSIONSAVAILABLE, EBP; Full SSE and SSE-2 Require OS Support for Test Eax, 00000030h JZ Nocheck Call CpuCheckforssesupportnocheck: Pop Ebx Pop ESI POP EDI POP EBP RET}} Author BLOG:

http://blog.9cbs.net/firetoucher/

related articles

Fast Memory Copy Code CPU Support Code Wide Band Delphi Estimation Process VI Command List Intercepting and Managing Windows