#ifndef CPU_SUPPORT_H # Define CPU_SUPPORT_H
#define CPU_SUPPORTS_CPUID (0x00000001L) #define CPU_SUPPORTS_FPU (0x00000002L) #define CPU_SUPPORTS_MMX (0x00000004L) #define CPU_SUPPORTS_INTEGER_SSE (0x00000008L) #define CPU_SUPPORTS_SSE (0x00000010L) #define CPU_SUPPORTS_SSE2 (0x00000020L) #define CPU_SUPPORTS_3DNOW (0x00000040L) #define CPU_SUPPORTS_3DNOW_EXT (0x00000080L)
Long cpugetsupportedextensions ();
#ENDIF ------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------------------- ------------ # include
Static long g_lcpueXtensionsavailable;
// this is ridiculous ???
Static long cpucheckforssesupport () {__TRY {// __ASM Andps XMM0, XMM0
__asm _emit 0x0f __asm _emit 0x54 __ASM _EMIT 0XC0
} __Except (EXCEPTION_EXECUTE_HANDLER) {// The operating system does not recognize andps Reset them if (_exception_code () == STATUS_ILLEGAL_INSTRUCTION) g_lCPUExtensionsAvailable & = ~ (CPU_SUPPORTS_SSE | CPU_SUPPORTS_SSE2);..}
Return g_lcpuextensionsavailable;}
Long __declspec (naked) cpugetsupportedextensions () {__ASM {Push EBP PUSH EDI PUSH ESI PUSH EBX
XOR EBP, EBP; CPU Flags - IF WE DON't Have CPUID, We Probably; Won't Want To try FPU Optimizations.
CHECK for cpuid.
Pushfd; Flags -> Eax Pop Eax or Eax, 00200000H; Set the ID Bit Push Eax; Eax -> Flags Popfd Pushfd; Flags -> Eax Pop Eax and Eax, 00200000H; ID Bit Set? JZ Done; NOPE ...
CPUID EXISTS, Check for Features Register.
MOV EBP, 00000003H XOR EAX, EAX CPUID OR EAX, EAX JZ DONE; No Features Register ?!?
Features Register EXISTS, LOOK for MMX, SSE, SSE2.MOV EAX, 1 CPUID MOV EBX, EDX AND EBX, 00800000H; MMX IS Bit 23 SHR EBX, 21 or EBP, EBX; SET BIT 2 IF MMX EXISTS
MOV EBX, EDX AND EDX, 02000000H; SSE IS Bit 25 SHR EDX, 25 NEG EDX AND EDX, 00000018H; Set Bits 3 and 4 if SSE EXISTS OR EBP, EDX
And EBX, 04000000H; SSE2 IS Bit 26 SHR EBX, 21 and EBX, 00000020H; SET BIT 5 or EBP, EBX
Check for vendor feature register (k6 / attlon).
MOV EAX, 80000000H CPUID MOV ECX, 80000001H CMP Eax, ECX JB DONE
Vendor Feature Register EXISTS, LOOK for 3DNOW! And Athlon Extensions
MOV EAX, ECX CPUID
MOV EAX, EDX AND EDX, 80000000H; 3DNOW! IS Bit 31 SHR EDX, 25 or EBP, EDX; SET BIT 6
Mov Edx, Eax and Eax, 40000000H; 3DNOW! 2 IS Bit 30 SHR EAX, 23 or EBP, EAX; SET BIT 7
And EDX, 00400000H; AMD MMX Extensions (Integer SSE) IS Bit 22 SHR EDX, 19 or EBP, EDX
DONE: MOV EAX, EBP MOV G_LCPUEXTENSISISAVAILABLE, EBP
Full SSE AND SSE-2 Require OS Support for the XMM * Registers.
Test Eax, 00000030h JZ Nocheck Call CpuCheckforssesupportnocheck: Pop EBX POP ESI POP EDI POP EBP RET}}
