This assessment note includes three parts:
1. Assessment description
2. Assessment content and requirements
3. Test type and answer
1. Assessment description
(1) Assessment target: Undergraduate student in computer science and technology.
(2) The proposition basis; the requirements of the teaching outline of computer science and technology (undergraduate) "computer system structure" class.
(3) Assessment requirements: This course is divided into three levels for the undergraduate student of computer science and technology. The specific assessment requirements are divided into 3 levels (see the appraisal requirements):
grasp;
understanding;
To understanding;
(4) Assessment method:
The method of combining the formive assessment and the end of the final termination appraisal, that is, the final results of the final exam, the final achievement or ultra-transformation is passed. The usual grade (operation, teaching experiment) accounts for 20%; the final exam accounts for 80%, and the test exam is taken, the time is 120 minutes.
2. Assessment content and requirements
The requirements of the teaching outline of the computer science and technology (undergraduate) "computer system structure" class. Every chapter of the teaching materials has a teaching requirements and the guidance part. After each chapter, there are homework and thinking questions. The assessment content and requirements are subject to the specific provisions of the textbooks, and the type of test questions given below and the reference answer will be fully reflected.
2. Assessment specific requirements
Chapter 1 Basic Concept of Computer System Structure
Master: Computer System Hierarchy, System Structure Composition, Implementation and Triple Relationship, Transparency, AMDAHL Law, CPU Performance Formula, Partial Principle, MIPS, and MFLOPS Definition.
Understanding: System Structure Classification, Von Nomanian Computer Characteristics.
Understanding: the development, price, application, and VLSI nuclear algorithm of computer system on system structure.
Chapter 2 Instruction System
Master: The definition and characteristics of RISC, reduce the method of instruction average execution cycle.
Understanding: Delayed Transfer Technical Command Cancellation Technology, Overlapping Register Window Technology.
Understand: Instruction Flow Adjustment Technology, RISC Optimization Compile Technique.
Chapter III Storage System
Master: The definition of storage systems, performance parameters of storage systems, address images and transformation methods, replacement algorithms, Cache memory work, virtual memory works.
Understand: Low cross access memory, high cross-access memory.
Understanding: Cache Analysis, Cache Write, Segmentation Storage System, Buffering on Virtual Storage System Performance, Replacement Algorithm Implementation Method.
Chapter IV Scale Processing Machine
Master: Working principle, time and space map, linear pipeline, input task continuous situation, the throughput rate, acceleration ratio and efficiency of linear pipeline, efficiency, and performance analysis of ultra-standard processing machine?
Understand: Input task discontinuous, single function, and linear pipeline performance analysis.
Understand: Overcaps, ultrafur, superclatrifidal supercurrent water treatment machine typical structure, pipeline structure of pipeline computer, control method of pipeline interruption, and development of pipeline technology.
Chapter 5 vector processing machine
Master: Vector Treatment, Three Vector Processing, Memory - Memory Structure, Register - Register Structure.
Understanding: Link Technology.
Understand: Vector processing machine data structure and access mode, coprocessor, vector processor instance.
Chapter 6 Interconnected Network
Master: The role of interconnection network, static network, dynamic network.
Understand: Storage Forwarding Forward, insects, the line switch is diagrand, and the virtual straight-through finding.
Understand: Interconnect functions, virtual channels, unicast, broadcast, broadcast, conference, channel traffic, network communication delay seventh chapter parallel processor and multiprocessor
Master: Sharing the storage multiprocessor, distributed storage multiprocessor, multiprocessor system, SIMD computer basic structure and its advantages.
Understand: SIMD computer instance, multi-process machine instance.
Understand: SIMD computer model, parallel algorithm, virtual shared memory, multiprocessor performance model, multiprocessor's Cache consistency, monitor protocol, directory-based protocol, MPP, SMP, and cluster system.
4. "Computer System Structure" Test Type and Solution
1. (20 points) explain the following terms
(1) (2 points) interconnection network
(2) (2 points) AMDAHL law
(3) (2 points) distributed storage multiprocessor
(4) (2 points) CACHE memory
(5) (2 points) Virtual memory
(6) (2 points) transparency
(7) (2 points) LFU algorithm
(8) (2 points) RISC
(9) (2 points) over-scale processing machine
(10) (2 points) Register - register structure
[answer]
(1) Interconnection Network: Interconnecting network is a network consisting of a switching element in accordance with a certain topology and control mode for implementing a small interconnection between multiple processing machines or multiple functional components within a computer system.
(2) AMDAHL Law: A component in the system is related to the use of the entire system performance of the entire system after a faster execution method is related to the ratio of the execution mode or the proportion of total execution time.
(3) - (10)..
Knowledge points for assessment: (1) Some basic problems and concepts of computer system structure research.
2. (20 points, each empty one point) fill in the blanks
(1) according to Flynn classification, depending on the organization of the instruction stream and data stream, the structure of the computer system can be divided into _____, _____, and _____ _____.
(2) In the CISC, the use frequency of various instructions is varied, and there is a result of substantially the following results. About the _____ (scale) instruction is high, occupying the processor time of _____ (scale).
(3) Partial principle of access is divided into both ____, both of the topical sectors of _____.
(4) According to the different address maps and address transformation methods, the virtual memory currently uses the virtual memory mainly ____, _____ and _____.
(5) From different angles, we can divide the pipeline into different categories. If there is a feedback signal according to the function segments of the pipeline, it can be divided into _____ and _____; multi-function pipeline can be divided into two types, that is, whether it can be connected in a variety of ways in the same time, can be divided into _____with_____.
(6) The interconnected network can be divided into _____ and _____ two categories, with a dedicated linking path between the respective nodes of the former, and cannot be changed in operation, and the latter is provided with an active switch, which can be Reorganization of the path. The message finding method includes two, namely, line exchange and package exchange. Where the package exchange includes _____, _____ and _____, etc..
[answer]
(1) SISD SIMD MISD MIMD or single instruction flow single data stream single instruction flow Multi-data flow multi-instruction flow single data stream multi-instruction flow multi-data stream (answer order can be different)
(2) 20% 80%
(3) Time space (the order of answer can be different)
(4) Type virtual memory segment virtual memory segment page virtual memory (the order of answer can be different)
(5) Linear pipeline nonlinear pipeline static pipeline dynamic pipeline (the front two answers can be exchanged, the two answers can also be exchanged) (6) Static network dynamic network storage forwarding finding virtual straight-through find diachodic diachids (front two The answer can be exchanged, and the three answers later can also be exchanged)
Knowledge points for assessment: (1) Some basic problems and concepts of computer system structure research.
3. (15 points) There is a two-layer memory hierarchy: M1 and M2. The hit rate of M1 is represented by h, and the cost of C1 and C2 are the cost of each kilobyte, S1 and S2 are memory capacity, T1, and T2 for access times.
(1) (7 points) Under what conditions, the average cost of the entire memory system is close to C2?
(2) (8 points) What is the time ta of the memory effective access time ta?
[answer]
(1) The average cost of the entire storage system is: it is not difficult to see: When S1 / S2 is very small, the value of the above formula is about C2. That is: S2 <
(2) TA = H1T1 (1 - H1) H2T2 Since H2 is equal to 1, TA = HT1 (1 - H) T2 assessment of knowledge points: (1) The average cost and effective access time of the storage system, (2 The concept of the storage system and the calculation of its performance parameters. 4 (15 points) Assume that the execution process of one instruction is divided into "Take Directive", "Analysis" and "Execute" three sections, each segment is DT, 2DT and 3dt. In various cases, the time expressions required to continuously execute the N instructions separately. (1) (7 points) order execution method. (2) (8 points) "Take Directive", "Analysis" and "Performance" overlap. [Answer] (1) When each instruction is executed, each instruction is used to use = DT 2DT 3DT = 6dt, so the time required for N instructions = 6N * DT (2) The first instruction is required to complete the required time = DT 2DT 3DT = 6dt, due to the "Directive" and "Analysis" phase of one instruction overlap the "Perform" phase of the next instruction, thereafter, after each 3dT is completed, the remaining N-1 instructions are used (N-1) * 3dt. Therefore, the time required for N instructions = 6dt (n-1) * 3dt = 3 (n 1) DT assessment of the knowledge point: (1) The basic concept of the pipeline, and the comparison of the order execution method. 2) The calculation time, efficiency, and acceleration ratio of simple flow water lines. 5 (15 points) Assume that the main memory of the computer is tissue, the block size is 8 words. The cache has 8 blocks. Painting the following mapping method from the main memory to the cache mapping relationship. Picture all mappings as clearly as possible. (1) (7 points) direct mapping. (2) (8 points) full-phase mapping. [Answer] (1) Direct Mapping Method (2) Learn Points for Full Lenovo Mapping Method: (1) Principle and Composition Structure of Cache, (2) Different mappings between cache and main memory. 6 (15 points) run 8 × 8 matrix multiplication c = a × b on the process of the following different structures, calculating the minimum time required. Only the execution time of the multiplication command and the addition instruction, does not calculate the execution time of the number of operations, data transfer, and program control. The delay time of the addition component and the multiplication component is 3 clock cycles, and the addition instruction and multiplication command must pass through a "tether" and "instruction decoding" clock cycle, each clock cycle is 20ns, and C. The value is "0". The output of each operating member has a direct data path to connect to the input of the operating unit, and a buffer register is provided with a sufficient capacity at the output of the operating unit. (1) (7 points). There is only one universal operating component in the process, and the instruction is performed in order. (2) (8 points). Snexing water line scalar processor, there is a static pipeline of two functions, the delay time of each function segment of the pipeline is a clock cycle, the addition operation, and multiplication operation passing through three function sections. [Solution] To complete the above matrix multiplication, we can calculate the number of various operations that need to be completed (assuming A and B are 8 × 8 matrices.
