I. CPU Terminology Explanation 3DNOW !: (3D NO WAITI) AMD Development SIMD instruction set, can enhance the speed of floating point and multimedia operation, and its instruction is 21. Alu: (Arithmetic Logic Unit, Arithmetic Logic Unit) In the processor is used to calculate, with its own data transmission unit and branch unit. BGA: (Ball Grid Array, Spherical Matrix) A chip package form, Example: 82443bx. BHT: (Branch Prediction Table, Branch Prediction Table) The processor is used to determine a numerical table in the direction of the branch action. BPU: (Branch Processing Unit, Branch Processing Unit) The area used to make branch processing in the CPU. BRACH PEDICTION: (Branch Prediction) A advanced data processing method starting from the P5 era, determines the direction of the program branch, and can operate faster than the CPU. CMOS: (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) It is a special chip, the most common use is the BIOS (Basic Input / Output System, Basic Input / Output System). CISC: (Complex Instruction Set Computing, Complex Instruction Set Computer) For longer instructions, called complex instructions relative to RISC Such as: x86 instruction length is 87 bits. COB: (Cache On Board, the integrated cache) The integrated cache is integrated on the processor card, usually refers to a secondary cache, an example: Pentium II COD: (Cache on Die, the chip integrated cache) inside the processor chip Integrated cache, usually refers to a second-level cache, an example: PGA Celeron 370 CPGA: (Ceramic Pin Grid Array, Ceramic Needle Raster Array) A chip package form. CPU: (Center Processing Unit, Central Processor) The brain of computer system, is used to control and manage the operation of the entire machine, and perform computing tasks. Data Forwarding: (Data Pre-Administration) CPU Copys the output value of one unit to the input value of the output value of one unit in one clock cycle. Decode: (Instruction Decoding) Due to the inconsistency of the X86 instruction, "translation" must be used in a unit, and the real kernel works by post-translational requirements. EC: (Embedded Controller, Embedded Controller) In a set of specific systems, the control device that has been added to a fixed position, and the control device that completes a certain task is called an embedded controller. Embedded Chips: (Embedded) A special CPU, usually in a non-computer system, such as a household appliance.
EPIC: (Explicitly Parallel Instruction Code, Parallel Instruction Code) Intel's 64-bit chip architecture, itself cannot perform x86 instructions, but can be compatible with the old X86 instructions through the decoder, but the operation speed is more than the real 32-bit chip. decline. Fadd: (Floationg Point Addition, floating point) FCPGA (Flip Chip Pin Grid Array) A chip package form, an example: Pentium III 370. FDIV: (Floationg Point Divide, floating point) FEMMS (Fast Entry / EXIT MULTIMEDIA State, fast entry / exiting multimedia State) In most Pentium, MMX and floating point units cannot run at the same time. The new chip speeds up the switch between the two, which is femms. FFT: (Fast Fourier Transform) A complex algorithm that tests the floating point capability of the CPU. FID: (FID: FREQUENCY IDENTIFY, frequency identification number) Pentium III to check the CPU frequency through the ID number, can effectively prevent Remark. FIFO: (First Input First Output, first-out queue) This is a traditional sequential execution method, first entering the instructions to complete and retract, followed to execute the second instruction. Flop: (Floating Point Operations Per Second, floating point operation / second) calculates a unit of CPU floating point capabilities. Fmul: (Floationg Point Multiplication, floating point) FPU: (Float Point Unit, floating point operation unit) FPU is a processor dedicated to floating-point operations, the previous FPU is a separate chip, after 486, Intel puts FPU With integrated in the CPU. FSUB: (Floationg Point Subtraction, floating point) HL-PBGA: (Surface adhesive, high heat resistant, lightweight plastic spherical matrix package) A chip package form. IA: (Intel Architecture, Intel Architecture) X86 chip structure developed by Intel. ID: (Identify, Identification Number) is used to determine the identification code of different chips. IMM: (Intel Mobile Module, Intel Mobile Module) Intel Develops processor modules for laptops, integrated CPUs and other control devices. Instructions Cache: (Instruction Cache) Since the speed of the system is slower, when the CPU reads the instruction, the CPU will stop waiting for memory transmission.
The instruction cache adds a fast storage area between the main memory and the CPU, even if the CPU does not require an instruction, the main memory will automatically send the instruction to the instruction cache. When the CPU requires the instruction, you can directly from the instruction cache. Read, no need to access the main memory, reduce the Waiting time of the CPU. Instruction Coloring: (instruction classification) A technique for manufacturing predicting execution instructions, once predicts that it is determined that the corresponding instruction decision is predicted, the processor will process the same judgment of the same intersection. INSTRUCTION ISSUE: (Instruction Send) It is the first CPU pipe for receiving instructions sent by memory and sent it to the execution unit. IPC (Instructions Per Clock Cycle, Instruction / Clock Cycle) Indicates the number of instructions that can be completed in one clock cycle. KNI: (Katmai New Instructions, Katmai New Command Set, SSE) Latency (latency) is more difficult, in fact, in fact, it indicates that the clock cycle required for a directive is fully executed, the less the incubation period is, the better . Strictly speaking, the incubation period includes an instruction from receiving the entire process of sending. Most X86 instructions today require approximately 5 clock cycles, but some of these cycles are overlapping with other instructions (parallel processing), so the incubation period of CPU manufacturers is longer than the actual time. LDT: (Lightning Data Transport, Lightning Data Transfer Bus) K8 Novel Data Bus, Froquency Foundation 200MHz. MMX: (MultiMedia Extensions, Multimedia Extensions) Intel Development The first SIMD instruction set can enhance the speed of floating point and multimedia operations. Mflops: (Million Floationg Point / Second, Million Floating Point Action) Calculates a unit of CPU floating point capabilities, which is based on millions of instructions. Ni: (Non-Intel, Non-Intel Architecture) In addition to Intel, there are many other manufacturers who produce X86 systems. Due to patents, their products and Intel are different, but they can still run X86 instructions. Olga: (Organic Land Grid Array, Substrate Grid Array) A chip package form. OOO: (Out of Order) One of the properties of the POST-RISC chip, it is possible to complete the calculation task in order to provide in the order provided, is an architecture that speeds up the processor calculation speed. PGA: (PIN-Grid Array, Pin Grid Array) A chip package form, a disadvantage is that power consumption is large. POST-RISC: A new type of processor architecture, its kernel is RISC, and the periphery is CISC, combined with the advantages of two architectures, with advanced features such as predictive execution, processor reunification, such as: Athlon. PSN: (Processor Serial NumBers, processor serial number) Identifies a set of numbers of processor features, including clocked, production date, production numbers, etc.
PIB: (Processor In A Box, Boxing Processor) CPU Manufacturer is officially launched on the market, usually more than the OEM (Original Equipment Manufacturer, original equipment manufacturer) vendors to expensive, but only PIB has The manufacturer's official warranty rights. PPGA: (Plastic PIN Grid Array, Plastic Needle Matrix Package) A chip package form, the disadvantage is that the power consumption is large. PQFP: (Plastic Quad Flat Package, Plastic Square Planic Pack) A chip package form. RAW: (Read after Write, Write) This is an error in the CPU's chart, that is, before the necessary conditions are not established, the final result is wrong. Register Contention: (Preemption Register) When the last write backward task of the register is not completed, another instruction exists conflicts when this register. Register Pressure: The number of registers required when the software algorithm is executed is restricted. For X86 processors, the register has become the biggest feature of its maximum, so AMD wants to increase the number of registers in the next generation chip K8. Register Renaming: (Register Rename) relocates the output value of an instruction to an arbitrary internal register. In the X86 architecture, this type of situation often occurs, such as: When a FLD or FXCH or MOV command requires the same target register, it is necessary to use it to the register rename. Remark: (Chip Frequency Heavy Identification) Chip Manufacturers set most of the CPUs to freely adjust multiplier and inferior frequency, which is selected in the same batch of CPUs in the same batch of CPUs. Level 1, low performance, is completed in the factory, and is a legal frequency positioning method. But after the factory, the dealer passed the low-end CPU overclock, and the new label was posted, and the illegal frequency positioning as a high-end CPU was called Remark. Because manufacturers have power to change their products, the dealers do this is copyright infringement, don't think that only software has copyright, hardware has copyright. Resource Contention: (Resource Conflict) When an instruction requires a register or pipe, they are used by other instructions, and the processor cannot respond to instantly, which is the resource conflict. Retirement: (Instruction Remove) When the processor performs a command, it automatically removes it from the schedule process. If only the instruction is completed, but still stay in the scheduling process, it is not an instruction to retreat. Risc: (Reduced Instruction Set Computing, Reximel Instruction Set Computer) A computer with a shorter length, which is running fast than CISC. Sec: (Single Edge Connector, Unilateral Connector) A module of a processor, such as Pentium II.
