Memory Management and TLB
We tend to explore most of the topics in this book directly from the most underlying, which seems to be naturally natural for a book that is concerned about the computer underlying architecture. However, in order to clear the memory management hardware, we have to start from the Unix style virtual storage system for the MIPS R2000. Behind this chapter we will discuss how the same hardware works in other environments.
Early MIPS CPUs are positioned to support applications running on UNIX workstations and servers, so memory management hardware is conceivable to help BSD UNIX - a operating system that has been perfectly designed and has full multi-virtual storage needs. Typical - Provides hardware for memory management functions. It is apparent that these designers are very familiar with the DEC VAX small machine, and many of the complex design is also abandoned while obtaining many ideas from this architecture. Especially many VAX use microcodes to solve problems, which are handled in MIPS.
In this chapter, we will start from MIPS design starting, facing a UNIX type operating system and its virtual requirements. We will show how MIPS hardware meets these needs. At the end, we will discuss that several ways you can take in the embedded system that cannot be used in the use of memory management hardware.
Memory address translation hardware (below, we will call it MMU, all known as Memory Management Unit) There are several different uses:
N relocation: The function method of the program and the pre-declared data address are determined during the compilation period, and the MMU allows the program to run in any physical address.
n For program allocation memory: MMU can create a continuous program space from many scattered pages in physical memory so that we can allocate memory from a pool full-size page. If we keep the memory block that releases the size of the different size, we will touch the debris problem: We have to stop in a memory space covered with "small islands", which cannot meet the application requirements for larger blocks, even if this is afraid of this All free space is sufficient.
n Hide and Protection: User-level programs can only access data within the KUSEG memory area (lower program address). Such procedures can only be obtained in the memory area licensed by the operating system.
In addition, each page can be independently specified as scriptable permissions or write protection permissions; the operating system can even stop an unexpected application to override the code space.
n Extended Address Space: Some CPUs cannot directly access all physical space they have. Although the MIPS I series CPU is a real 32-bit architecture, they lay out of address mapping, so that unmapled address space windows Kseg0 and KSEG1 (they do not rely on MMU to perform address translation), 512M in the beginning of the start of physical memory . If you have to access a higher address, you must pass by MMU.
n Memory maps Adaptation to the program: With the help of the MMU, your program can use the address suitable for it. Many copies of the same program may run in a huge operating system at the same time, making them easier to use the same program address.
n Page capabilities: The program can seem to be as normal as all resources they apply, and the operating system is actually only assigned to their current resources. Programs accessing unallocated space can cause an exception (Exception) that is handled by the operating system, and the operating system is in this memory to load the appropriate data and make the application continue to run.
The nature of UNIX memory management is to run numerous tasks (ie Multitasking - multi-process), and each task each has its own memory space. If this work is successfully completed, then the fate of each task will be independent of each other (the operating system itself is also protected): A task itself crashes or the wrong doing something will not affect the entire system. Obviously, this is a very useful feature for universities using the distribution terminal to run the student programs; but not only that, but not only the most stringent commercial system environment also needs to support experimental software or prototypes while running. The software is commissioned and tested. The MMU does not only benefit the small embedded programs in order to establish a huge virtual storage system, and the small embedded program can also benefit from reacting and more efficient memory allocation. If you can map the address on the application concept to any available physical address, the system runs more easier at different times.
Multi-process and isolation of different processes have been transplanted on smaller computers. At present, they are now very common in personal computers and Internet servers.
Embedded applications often use multi-process mechanisms, but there is almost no more embedded operating system uses isolated address space. Perhaps this is considered to be less important in the embedded CPU and the operating system thereof and the above operating system.
MIPS is so necessary to lead to a low-cost mechanism of the workstation CPU in 1986, may also be confirmed to have a certain relationship with the rise of embedded systems in the late 1990s. Even a small application, is also troubled by the rapidly growing code size, you need to use all known means to control the complexity of the software; this flexible software-based approach created by MIPS can provide any required space. Just a few years ago, the CPU's manufacturers were difficult to determine if the MMU is worthy of inclusion in the positioning embedded market; however, until 1997, Microsoft's WINDOWS / CE that cannot be run without memory management hardware, has been It is deemed to have a successful solution for the various difficulties faced by embedded.
6.1 Memory Management on Large Computers
Perhaps the entire work from a memory management system similar to a UNIX system is the easiest (select UNIX as a study because it is large, but is simpler than the operating system on the PC). Typical features are shown in Figure 6-1.
6.1.1 Basic Process Space Layout and Protection
The widest partition line in Figure 6-1 is in the part of the low half-indicated "user program accessible" - and the remainder. The user accessible part of the program's space is part of our typically referred to as "kuseg" in the MIPS memory map described in Section 2.8. All high address memory is reserved to the operating system. From the perspective of the operating system, the lower half of the address is a secure "sandbox" (Sandbox) that can be used by the user program. If the program runs an error and destroys all the data itself, other programs don't have to be affected.
From an application's point of view, this area can be used to create an exclusive complex data structure to continue your work.
Inside the user area, that is, in the inside of "sandbox", the operating system provides more stack spaces to the needs of the program (due to the stack in the dark down). It also provides a system call to use the "Declared Data" maximum address as the start address and growing address space - people call it "Heap" (HEAP) Get more data space. "Heap" is used to implement library functions such as Malloc () to provide large block additional memory for applications.
The memory blocks used to build a stack and stack should be small enough to save the system to save memory, but it must also be large to avoid excessive system calls or the generation of abnormalities. However, when each system calls or visits anomalies, the operating system will have the opportunity to monitor the memory consumption of the application. Operating systems can enhance restrictions to ensure that applications do not get too much memory to threaten key running activities in the system.
In a UNIX type system, the process has its own identifier in the operating system kernel; in order to ensure that the application can only do what they are allowed, most of the kernel services are available in the form of a special child function (ie system call). The application call must also follow certain special provisions. Figure 6.1
Operating system's own code and data clearly cannot be accessed by user space. In some systems, this is done by putting them completely in an isolated address space; the operating system running on the MIPS share the same address space with the user program, when the CPU runs under user-level privileges, The space accessed is illegal and will result in an exception.
It should be noted that although the user space of each process is mapped to physical storage space specially in this process, the space of the operating system is often shared. Most operating system codes and resources are in all processes. It seems that the operating system kernel is a multi-line single address space - and the user address space of each process is located exclusive to its own isolation space. The running process issued by the application in the kernel is completely trustworthy, and the application does not need to be trusted.
The effective part of the user space is separated, the stack is located at the top of the space, and the code and static compiler are located at the bottom. This allows the stack to grow down (this is implicit, due to the accumulation of the function parameters in the run of the program), the data space can grow up (this is explicit, since the program calls the library function to allocate memory). The operating system can allocate more memory to the stack or data space and map to the appropriate address.
Note that in order to enable the program to use large data space, the stack will usually grow downward from the highest address allowed by the user space. This address map feature should be properly cope with address space (there is a huge hollow in the spaced space) in the address translation scheme.
In real time, the mechanism is more complicated in order to seek efficiency and more shared functions. Most systems map the application's code to "read-only", which means that these code can be shared by many process secure - many processes run the same application.
Many systems not only share the entire application, but also to share blocks (shared libraries) through library calls (shared libraries). At present, we still don't discuss the other big pile of questions triggered.
6.1.2 Map Processes Space to Physical Memory
What mechanism needs to support this model?
The address space of the MIPS architecture or less requires the program (whether the application is still the kernel method) is fixed during the compilation connection. This means that the application is not possible to use different addresses when constructing - is also the case when we want to run the same application. Therefore, when the program is run, its address is mapped to a physical address that has been fixed by the operating system when the program is loaded.
Although updating all address mapping information is feasible when switching in process context, it is quite low. The alternative is: We give each process (called "process ID in Unix, but more accurate call should be" address space id "or simply referred to as" ASID "). Any address in each process produces a unique to-switch address after the ASID extension of the process is expressed. ASID needs to load a register of the CPU when the process is implemented, so that the hardware can be used.
The mapping mechanism also allows the operating system to distinguish the different parts of the user space to be treated: some space of the application (generally the code portion) is mapped to read-only, and other parts can be missed and accessible can be caused "Trapped", which means that a loose running program can be stopped earlier.
The kernel portion in the process address space is usually shared by all processes, and most of this part maps to resident operating system code and data. Since these code is connected to these addresses, there is no need for a flexible mapping mechanism, and the kernel running on MIPS will put their most of the code in this architecture has a fixed mapped address space in this architecture. 6.1.3 page mapping is best
In order to map the address people try a lot of special methods, usually use the "base address / range" binary group to ensure the correctness of the address. However, if the memory mapping is provided to the program to suit the size of the size it needs, although this is clearly providing the best service to the application, it will quickly lead to the available memory to zerozoate memory. Shred. All actual systems are mapped to the page (PAGE, a fixed size memory block). The page is usually 2 power size, 4K size gets the frequency of use of an overwhelming advantage.
In the case of 4K, a CPU address can be simple mapping:
Several portions of the "Top Address WITHIN PAGE section" do not need to translate, so the memory management device only needs to deal with the translation of the address high, that is, referred to as "virtual page number" (Virtual Page Number in the figure. " The part of the referusion is the high level of the actual physical address (ie Physical Frame Number, or "PFN, no one can think of it is not called PPN).
6.1.4 We really want
The mapping mechanism must enable a program to assert an address within its own process space or address space, and can efficiently convert it to a real physical address to access memory.
A good idea is to use a table (ie, page table) containing all pages in the entire space, each entry contains the correct physical address of this page. This is obviously a considerable data structure, so it has to be stored in the main memory. However, this brings two serious problems.
First, we need to access two memory each time we take out or deposit data, which is obviously nothing to expect in performance. You have foreseen such an answer: We can use a cache to store these portals, just access the resident memory when we missed frequently. Since each sabted entry covers 4KB memory space, we seem to be able to get a unsteady, and it is quite small and quite small. (Now you want to introduce it, it is very sparsely and sometimes called "Lookside Buffers), so memory translation is called" Translation Lookaside Buffaside or "This abbreviation More commonly used).
The second problem is the size of the page table; a space for a 32-bit application divided into a 4kB size page will result in a 10,000 portions, which will occupy nearly 4MB of memory. We need to find some ways to make this table small, otherwise there will be no more memory to use it.
We will discuss different solutions in such a premise: Real running programs have huge address empty holes in address space, if we can have a way to avoid these voids in the table in physical memory, It seems to be much better.
Now we have a solution, essentially, from the memory translation system used by DEC on the VAX miniature, which brings a far-reaching influence on the vast majority of concurrent architecture. It is summarized in Figure 6-2.
Figure 6.2
The hardware processing process is roughly like this:
n One virtual address is divided into two parts, low half address bits (usually 12 digits) without translation, so translation results always fall within a page (usually 4KB). N high half address bits, that is, VPN, will form an ASID that is currently running the process to form a unique page address.
n We look for whether there is a translation item in this page in TLB. If so, then we will get the high position of the corresponding physical address, eventually get the available address. TLB is a storage device for special purposes, which can use various effective ways to match the address. It can refer to a global flag bit to ignore the ASID bit when looking for some ports, so these TLB portals can be used to map a certain segment space in all processes.
Similarly, VPNs can also use certain mask bits when stored, so that some bits in the VPN are excluded during the matching process, which enables the TLB entry to map a larger range of virtualities.
Both special mechanisms in some MIPS MMUs were adopted.
n Typically store some additional bit information (Flags) in the PFN to control which access can be allowed - the most obvious, allowing read operations without allowing write operations. We will discuss the marker of the MIPS architecture in Section 6.2.
n If matching failure in the TLB inlet, the system must be positioned or assigned an appropriate portal (corresponding information using the resident memory page table) and load it into the TLB, and then perform a translation process again
In the VAX miniature, this process is controlled by microcode, and the entire process is completely automated for programmers.
6.1.5 Origin of MIPS
In order to provide a set of VAXs as few of the use of VAX, MIPS designers need to find some good ways. It is unacceptable by microcode-controlled TLB re-load (REFILL), so they bravely take a step: hand over this job to software.
This means that in addition to having a register used to store the current ASID, the MMU device is just a TLB, that is, a simple high-speed, fixed length translation table. System software can (usually, this) uses the TLB as a quick-end table list, but the TLB hardware itself can not use itself as a quick memory, but only this: When an address cannot be performed When translating, TLB triggers a special exception (TLB reloading into an abnormality) to raise the calling software program. However, TLB's detail design and corresponding control registers have a very careful consideration to help software more efficiently.
6.2 Features of MIPS TLB
MIPS TLB is usually implemented on a chip: even in the event of a quick hit, the memory translation is still going on, so this is a very important "critical path" on the machine. This means that it must be small, especially in the early years, so it is very sensible to control its scale.
Basically this is a full-connected storage unit. Each entry is an associated memory with a key value (KEY) domain and a data domain; when a key value is provided, the hardware is matched and gives data in the entrance to success. Usually the full-connected memory efficiency is high but is too wasteful on hardware, and the MIPS series TLB contains 32 to 64 inlets; this size of the storage amount is relatively easy to handle in chip design.
The R4000 style CPU is now using such a TLB: Each inlet content is extended to 2 times to accommodate two consecutive VPNs of each mapping independent physical page. This pair of portions have only added little hardware logic but doubled the map pages that TLB can be loaded, avoiding significant adjustments to TLB design. You can see why it is called "fully connected", which emphasizes that all key values are actually parallel to compare the input values.
Figure 6.3
The entrance of the TLB is shown in Figure 6-3 (you can find a detailed programming information in the following 6.5). The key value of the TLB contains the following:
N VPN: The high position of the virtual address (ie the virtual page address). In the double entrance TLB, it is called VPN2, which is to emphasize if each physical page is 4KB, then a virtual address will remove the low position (these low positions are used to select the output domain on the left) to compare To select a pair of entrances.
N Pagemask: This has recent CPUs. It is used to control how many bits of virtual addresses to compare with VPN and determine how many bits are added to the real address; the larger the space to match the matched map of the less bit. The MIPS CPU can set an inlet mapping up to 16MB of memory. In the case of using various page sizes, they are used to select an odd number or an even number entry in the mask.
n asid: Marking this translation process belongs to a particular process, so it is not successful unless the current ASID of the CPU is consistent with it. This bit of "C" is set to 1, turn off the match match, which marks the translation of this translation can be performed in all process spaces (so this part in the address map is shared by all space), ASID bit In the early CPU, it is 6-bit length, while in the near future CPU is 8.
The TLB output unit will give the physical page number and a number of markers that are not large enough but sufficiently.
n Physical Page Number: 32-bit CPU only one n (noncacheable, not buffer) bit - 0 indicates that can be cached, 1 means it is not a cache.
The 64-bit CPU provides a 3-bit C domain to represent a wider range of values, which can notify the multiprocessor hardware to follow what protocols when accessing to page data shared with other processors. The 64-bit CPU does not have a 64-bit CPU in the hardware consistent protocol feature, which has the format of such a TLB entry; only 2 values in all R4000 types of CPUs indicate cache (3) or not cache (2) The latter is the standard default value in the R4000 type CPU. Modern embedded CPUs can use different values to choose different quick memory strategies: a pair is written and write back, another pair is written allocate and written Uncluded Write On Miss. Please check your CPU user manual for details.
N-write control bit (D): Set to 1 allows data to write to the corresponding page. "D" comes from its full name "dirty"; please find why you are in Section 6.8.
N Valid bit (V): If it is 0, the corresponding inlet is not available (not available for address translation). It seems that this is nothing to say: This is because the software that is reinstalled into the action is to optimize the speed and do not want to check the special case. When the program is required to perform some processing on the page before the program can use a page table table, the corresponding portal can be labeled as invalid (Invalid). When the TLB reloads, this will trigger a different type of fall, call a special program for processing, without having to test in each reinstalry incident. It is very simple to translate an address now, we can enrich the process described above as follows:
N CPU generates a program address: Whether it is to take instruction or loading and writing data, translation is performed as long as these are not in the special unmapped interval in the MIPS address space.
The low 12 bits are separated, and the remaining VPN and ASID of Entryhi are the key value of the TLB, and the PageMask bit in the TLB port is modified to this value.
N TLB for key value matching: The entry that matches success is selected. PFN is pasted before the lower position of the program address to produce a complete physical address.
Is the N address effective? The V-bit and D bit are referenced. If the address is invalid or is trying to write a page of a D bit is 0, the CPU generates a dropped action. Both the BadvadDR register in all translation fed into operations will be loaded into the procedure address; and in any TLB exception, the TLB's ENTRYHI register will be pre-loaded into the VPN of the plug-in program address.
Do not use the convenient register Context (XContext in the 64-bit CPU) in the case of TLB penalty, at other times they may be used to track things such as Badvaddr, or not, both are allowed.
N Is it cached? If the C bit is put, the CPU will go to the snap to find data copies in the physical address; if the data is not there, then it will go to the memory and leave a copy to the sailing. For the entry that the C bit is not placed, the CPU does neither find the sabo or not the data of the corresponding address.
Of course, the number of TLBs can only help you translate relatively small program address space - approximately hundreds of KB. This is not enough for most systems, and TLB is almost always used as a software to maintain a more huge translation set.
When a set of addresses in the TLB fail, it will fall into a TLB re-entered exception. System software needs to do the following:
n Judging whether there is a correct translation; if there is no existence, this fall will be sent to the program used to handle the address error.
n If there is a correct translation, create a TLB entry for implementing translation.
n If the TLB has been filled (it is basically always full in the running system), the software should choose a discarded entry.
N software fills the new entry content in TLB.
Take later on Section 6.7 to see how these is handling, but here, please note that although there is a special CPU characteristic to help achieve this type of reinstallation action, the software can also be reinstalled in the TLB in any way.
6.3 MMU register
Now we can finally collect this set of itself down, let us go deep into the details of MIPS. I hope that you have enough knowledge background to excavate the content in the text; once we stated the details, we will show how the corresponding device works.
Just like all other parts in the MIPS CPU, the control of the MMU is affected by a small amount of additional instructions and a small part of the number of registers in the set. Table 6.1 lists the control registers, we also need to use the instructions used in Section 6.4. Register Assist Merrator CP0 Register Number Entryhi Entrylo / Entries Entrylo1 PageMask
10 2
3 5 These registers have all set all the information required for a TLB entry. All read and write operations for TLB must pass them. Entryhi contains VPN and ASID; ENTRYLO contains PFN and some markers. In fact, the Entryhi (ASID) domain has 2 duties because it is responsible for remembering the current active asid. In some CPUs (so that there are 64-bit CPUs so far, each entrance maps 2 consecutive VPNs to different physical pages, independently specified by 2 registers called EnTrylO0 and Entrylo1. Entryhi has increased to 64 bits in the 64-bit CPU, but the 32-bit format is kept for software that does not need to use the long address. PageMask can be used to create an entry that can map more than 4KB pages; see Section 6.3.1. Index 0 is used to decide to read or write which TLB portal Random 1 when using the appropriate instruction (actually a free count counter) is used to let TLBWR to write a new TLB entry to a random selection location . Save time for processing that uses a random replacement software to save the TLB reloading an abnormality (perhaps no other suitable alternative). Context XContext 4 20 These are very useful registers that accelerate the process of TLB reloading. They are readable and writable, and the low range from cannot translate. The domain of the register is arranged such that if you use the appropriate memory translation record of the memory copy of the memory copy, then the Context will have a pointer to the page table record that is used to map trigger an exception address after the TLB reloading. . See Section 6.3.5. XCONText has done the same job when processing more than 32-bit valid addresses; Direct expansion of the Context register format is not performed due to the size of the data structure of the operation results. Software on some 64-bit CPUs is also happy to use 32 deficiency gauges, but when these are not enough, 64-bit CPUs are equipped with "mode bit" SR (UX) and SR (KX), they can cause an alternative The TLB reloading processing method is called; and this processing method can use XCONText to support a huge and manageable page table format.
Table 6.1
6.3.1 Entryhi, Entrylo and Pagemask Registers
Figure 6.4 shows these registers, which is also the only visible part of the programmer to TLB, and their design is also intended to be optimized.
Entryhi's content domain is explained below:
N VPN, VPN2 (virtual page number): These are the high part of a program address (ignore the remainder of 0-11 bits). VPN2 ignores 12 bits, because the port of the corresponding TLB will map a pair of 4KB virtual pages. This domain is automatically used to match the program address that cannot be translated. When you want to write a different TLB entry, or if you want to check the TLB content, you must manually set it. The 64-bit system (so far) does not really support the same huge virtual address space as implied above. VPN2 is actually a 27-bit domain in the R4x00 CPU to accommodate 40-bit program address space. The high position of the VPN2 must be written as a total of 1 or all 0, match the highest one of the corresponding ENTRYLO register; at the same time, the high level is 1 representative access is the kernel address space, otherwise the high is all 0.
If you only use 32-bit instructions, these are automated because all register values are included in this mode contain 64-bit symbol extensions for 32 digits. n asid: This is usually used to save the indication of the current address space seen by the operating system. An exception does not change it, so it still saves the correct identification information for the currently running process after a reinstallation of abnormality.
Most software systems deliberately write this domain to the current address space. However, you must be careful when you use TLBR to view the TLB entry; this action overwrites the entire Entryhi, so you must resume the correct current ASID after this.
N R: This is the address space identification. You can just look at another part of the address bit of Entryhi (VPN2); in fact it is just the highest bit of the 64-bit MIPS virtual address. However, if you can recall 64-bit MIPS expansion memory mappings (see Figure 2.2 in Section 2.2), you can find that these highs separate different access rights. At the same time, they differ from the high level of VPN2, because in fact they can use different value -Entryhi's part of the high position defined in the implementation must be 1 or all 0.
Figure 6.4
Entrylo's domain is explained as follows:
n PFN: This is the high level of the physical address translated accordingly by the VPN of Entryhi.
N n (inaccessible logo): Set to 0 to allow the corresponding address to be saved, 1 is not cached.
N c: For R4000 and later CPUs, memory access has a richer saving policy to select, which is encoded in a 3-bit length domain. However, in addition to the "non-cache" (2) and "multiprocessor non-signal cache" (3), there is different in an embedded CPU with a multiprocessor with an energy-saving consistency. How to use.
N D (DIRTY): This is used as a "write allowable" bit. It is set to 1 means that the write is allowed to be written. See Explanation of the term "dirty" in Section 6.8.
N v (Valid): If set to 0, then any address access of the entry will result in an exception. This can be used to represent a page currently inaccessible (in a pure virtual address system), or it can be used to represent a pair of translations at ENTRYLO.
N g (Global Bit): When a G bit of a TLB entry is set, the TLB entry will only use the VPN domain to match, regardless of whether the ASID domain of the TLB entry is consistent with the value within ENTRYHI. This allows us to implement a part of the address space to share in all processes without increasing additional pages.
n 0 domain: These domains have been 0, but they are different from many reserved domains, they don't need to be written as 0 (writing data will not have anything). This is very important; this means that the memory-generated memory-generating data used to generate ENTRYLO is resended in TLB can reserve some software to explain the data, and the TLB hardware ignores these fields without having to waste precious CPU time. Shield these bits away.
The PageMask register has been implemented in all 64-bit CPUs so far. The current MASK field is copied in the TLB entry, and the bit set to 1 will play a result of the virtual address to be ignored when the TLB entry is matched (and causes the one that does not modify it to the final physics. Address), this effectively helped match a larger capacity page. The bit in the address is also copied directly to the physical address. No MIPS CPU allows you to use any bit arrangement in Mask. Most of them are allowed page size between 4KB to 16MB, the page size is incremented by 4 times relationship:
NEC's VR4200 CPU only supports two pages of 4KB and 16MB, but the corresponding coding is fixed in the hardware.
6.3.2 INDEX register
The index register is used to specify the entry when you intend to write a specific TLB entry, and can also be used to return the corresponding TLB index after you use TLBP to find a certain translation.
As can be seen in Figure 6.5, INDEX is not just a number. The P-domain is set after the TLBP instruction looks for a legal translation failed; because it is the highest bit of the register, this result is like a 32-bit negative number, it is easy to check.
Note that the early MIPS CPU domains have different locations, and only 6 valid bits (maximum 64 TLB portals).
Figure 6.5
6.3.3 Random Register
The Random Register has index that counts when counting each instruction in the TLB (it is decremented, if this feature is important to you), it is an index of TLB when the TLB portal is executed This supports the random replacement strategy of writing TLB portals.
Usually you never need to read and write the Random Register (shown in Figure 6.6), but it may be useful during the diagnosis. We may expect that the hardware's random domain is set to the maximum value when the system restart (RESET) - is equivalent to selecting the TLB portal of the maximum number, and each clock cycle will be decremented, until a foundation value (Floor Value) Then, the value of the value of the wrap becomes 63, and the decrement is reduced.
Therefore, the TLB inlet from 0 to less than the base value is not affected by the random replacement, and the operating system can use these grooves as a permanent translation portrait - this is called "binding" in the MIPS operating system.
In the early CPU, the base value is fixed to 8, but the practice of setting a bit overbearing to this constant has incurred some complaints, so the 64-bit CPU introduces the Wired register, allowing to change the base value, and thus the Random register can be used Change.
Figure 6.6
6.3.4 Wired Register
This is just a value, but the bound value inside does not have meaningful effects when the binding value exceeds the TLB's highest index. When you write a Wired Register, the RADOM register automatically resets the maximum number of serial numbers to TLB.
6.3.3 Context Register and XCONTEXT Register
When a translation is not in TLB, the CPU cannot cause an exception, and the virtual address that cannot be completed will be stored in the BadvAddr register, and the VPN (part of the TLB cares) has also been deposited in the EntryHI register. Obviously, this has been done enough, but in order to accelerate an abnormal process, the Context and XContext registers will reassocate the same information in some format, so that a pointer value that can be used immediately for the memory page table. .
Figure 6.7 shows these registers, and the descriptions of each domain are as follows:
n Ptebase: This is a part that stores the positioning information you write. In order to achieve the reinstallation process of "standard", this should be the high level of the start address of the memory resident page table. The start address must select a 20th bit and the following bit of bit 0, because the Context register will be used to make a "logical or" operation, rather than doing addition. This limits the address of the memory reserved to start with a 1MB (doubt in the picture in the picture) on the virtual address - it is probably nothing to trouble. n Bad VPN / BAD VPN2: After an address exception, it will be loaded with the corresponding address (doubt, VPN is 20 digits in Figure 6.4, and the Bad VPN is 19-bit in Figure 6.7), and is in the BadvadDR register. The high is exactly the same. Why is VPN2? If your CPU's TLB is paired in the port, then the 12th bit of the address is not a TLB key value domain.
The value of VPN and VPN2 will be left in advance to pre-calculate a structural pointer having a length greater than 1 byte in advance. The 2-bit shift in the 32-bit CPU allows the 4-byte length of the inlet, which is sufficient to load the full multi-information to fill the ENTRYLO register for constructing the other half of the TLB entry. 64-bit CPUs not only have 64-bit ENTRYLO0 and ENTRYLO1 registers, must also have 2, because each TLB entry maps 2 pages; therefore, the page table must expect 16-byte long entry, VPN will move left 4 bit.
n 0 domain: These domains are always 0
Figure 6.7
6.4 MMU Control Directive
2 instructions below
TLBR # read TLB entry according to Index register
TLBWI # Write TLB inlet according to Index Register
The TLB portions and EntryHI selected in the INDEX register and the EntryLO registers are swapped in the ENTRYLO register.
You will not often need to read a TLB entry; when you do this, remember that you will overwrite the Entryhi (ASID) domain, which is set to be related to the address map of the current running process. So please write it back to the original value.
instruction
TLBWR # written to the TLB entry according to the Random register
The contents of Entryhi (including Asid), Entrylo, and Pagemask registers are copied to the TLB port indicated by the Random Register - if you use a random replacement policy that will save some time. In actual use, TLBWR will be used to write a new TLB entry in a TLB reissue in an abnormality process, using TLBWI in any other case.
instruction
TLBP # TLB Find
Finding the virtual page number and the inlet that match the contents of the content in the EntryHI register in the TLB, and store the index value of the corresponding entry into the Index register. If the match fails, the P bit of the INDEX register is set - this makes a negative value, which is easy to detect.
If more than one entry matches success, anything can happen. This is a serious mistake, and it will never appear in the normal situation.
Note that the TLBP instruction does not take data from the TLB; you must do this after running the TLBR (read the TLB content according to the index).
The TLB inside is flowing water, which masks this on the instruction surface for managing and checking. Many implementations require TLBP instructions to be kept closely to access memory operations.
6.5 TLB related programming
The TLB entry is set by copying the entry into the TLB appropriate position by filling the desired domain to the EntryHI and the ENTRYLO register and passing the entrance into the TLB appropriate position.
When you have reissued an exception in handling a TLB, you will find that Entryhi's content has been set up.
Be careful not to create two portions that match the same "address / asid" combination. If the TLB contains a duplicate entry, try to translate this address or look up this address potential to destroy the CPU chip. Some CPUs protect themselves by closing TLB in these situations, and the SR (TS) bit is placed. From this time until the hardware restart, TLB will not perform any matching. System software usually does not need to read TLB portals at all. However, if you want to read them, you can use the TLBP instruction to find a TLB portal with a specific address and see the result is reflected in the INDEX register. Don't forget to save the EnTryhi register and restore it after the lookup is re-recovered because it may be important.
You can use TLBR to read the contents in the TLB entry to EnTryhi and EnTrylo.
You can find that the TLB structure is divided into ITLB and DTLB in order to perform translation to the instruction and data address; these are small hardware control, which are completely transparent to the software.
6.5.1 How is resending?
When the program accesses any of the translated address area (usually under an protected operating system, kuseg is used for the application, while KDEG2 corresponds to the privilege of the kernel, if there is no corresponding translation record in the TLB, the CPU will trigger A TLB reloads an abnormality.
TLB can only map a small part of the modern server or workstation physical memory space. The large-scale operating system maintains a memory resident page table containing a large number of page translation information, and uses TLB to use TLB as a recent translation of translation. Most of the case The page table is an array of TLB portals that can be used immediately, you can use the context register as a pointer to it.
Since the MIPS system typically nucless the operating system core in the non-translation memory area KSEG0, it is usually a user-level program that needs to be translated into a KUSEG address. Several hardware features are designed to accelerate this usual treatment. First, these reinforcing anomalies are placed in a vector form in a memory low address that does not produce other abnormalities. Second, a series of delicate small tricks used in design makes the internal memory constitutive group table to be assigned in the kernel deficiency address (the corresponding part of the KSEG2 area or 64-bit system), so that the physical memory space does not need to store the page table. The "Empty" section used to map the process address space.
Finally, the Context and XCONTEXT registers can be used to access the correct ports in the memory resident page table.
We will analyze this process in detail in Section 6.7. But before we deeply explore, we should pay attention to all these features are "non-mandatory". In a small system, TLB can be used to create a fixed or rare change to translation devices for performing from program (virtual address) to real address translation, these cases don't even need to use it as a quick memory. .
Even the "standard" page table is not used in the implementation of some larger dummy operating systems on MIPS. Early versions of portable NetBSD kernel organizes a second-level cache for translation information for translation information in the usual software management, in the usual reinstalry entry code; access to its translation is not in the second level cache is very rare This will be transferred to a relative heavyweight process by C language, and extract information from a machine-independent page table.
6.5.2 Using Asid
We build TLB portals through a special ASID configuration and set the EnTrylo G bit to 0, unless the CPU's Entryhi (ASID) register field matches the corresponding value of the TLB entry, those portions will never fully match with a program address. of. This allows you to map 64 or 256 different address spaces simultaneously without having to completely clear the TLB during process switching. If you don't use Asid, you must traverse the entire TLB and cancel all of you don't use the ASID's mapping.
6.5.3 Random Register and Binding Portal
Hardware is not available to you to find the means of the most frequently used TLB entrance. When you use the TLB as a sohere to use and you need to load a new mapping, the only useful policy is to randomly replace an entry. The CPU has been easier to do this by maintaining a count (actually decremented) in each processor cycle. Randomly replaced a scary and low efficiency; you may just sacrifice the most frequently used entrance, and the entrance is almost in a short period of time. But in fact, when you have a considerable amount of optional victim, this situation does not often happen to bring real trouble, and most of the operating systems on MIPS have at least 40 sacrifices.
However, let some TLB portals are ensured until you take the initiative to remove it is often useful. This will be very good for maps that you are not known to usually use, but it is also very important because they make you map some pages and strictly ensure that no reload is available on these pages. abnormal.
These stable TLB portions are described as "binding": consisting of TLB 0 to 7 in the R3000 CPU, while in the R4x00 and subsequent CPUs in the slogan can be from 0 to any one you program Write the value of the Wired register. TLB itself does not do special treatment for these entrances; magic comes from the Random register, it will never take the value between 0 to "binding value); it starts directly from" binding value 1 "to it The maximum cycle change. Therefore, the usual random replacement does not affect the TLB entry between the serial number to the 0 to "binding value), which will always exist until it is clear until clearly removed.
6.6 Memory Translation: Settings
The following code segment is used to initialize TLB to ensure that it does not match any address located with KSEG2. We completed this initialization for R3000 and R4000 TLB, respectively. Below is a simple initialization action for the R3000 or similar CPU TLB:
#include
Leaf (MIPS_INIT_TLB)
MFC0 T0, C0_ENTRYHI # Save ASID
MTC0 ZERO, C0_ENTRYLO # TLBLO = VALID
LI A1, NTLBID << TLBIDX_SHIFT # index
Li A0, KSEG1_BASE # TLBHI = VPN in impossible
.set NoreOrder
1: SUBU A1, 1 << TLBIDX_SHIFT
MTC0 A0, C0_ENTRYHI
MTC0 A1, C0_INDEX
Addu A0, 0x1000 # Growth VPN, make all entrances
Bnes A1, 1B
TLBWI # in the DELAY SLOT jumped
.set reorder
MTC0 T0, C0_ENTRYHI # Restore ASID
J ras
End (MIPS_INIT_TLB)
Below is a simple example of a R4000 or a similar CPU TLB initialization:
#include
Leaf (MIPS_INIT_TLB)
DMFC0 T0, C0_ENTRYHI # Save ASID
Li A1, NTLBID # From the top of TLB 1 start Li A0, kseg1_base # Tlbhi = no possible VPN
MTC0 ZERO, C0_ENTRYLO0 # 0 is a non-legitimate value
MTC0 ZERO, C0_ENTRYLO1
1: SUBU A1, 1
DMTC0 A0, C0_ENTRYHI
DMTC0 A1, C0_INDEX
Addu A0, 0x2000 # Growth VPN, make all entrances
TLBWI
Bnes A1, 1B
.set NoreOrder
NOP # TLBWI later uses Entryhi
DMTC0 T0, C0_ENTRYHI # Restore ASID
.set reorder
J ras
End (MIPS_INIT_TLB)
Let's take a look at the initialization process of TLB.
n Both programs start from the top of TLB (constant NTLBID can be included in the header file in the algorithm is R3KC0.H or R4KC0.H)
N entrylo0 and 0 values in Entrylo1 means that any translation is not legal, but this is not enough to avoid the trouble of repeating the entrance.
n Note that INDEX in the R3000 version has a domain that needs to be shifted, so we cannot add only 1.
n The VPN stored in each inlet is the corresponding portion of the page in the KSEG1 area, which is defined as non-translation addresses and never look for. But even so, we still guarantee that all VPNs are different.
6.7 TLB exception code example
This program implements undoubtedly the translation mechanism designed by the user address in the UNIX type system structure designer. It relies on the mechanism of establishing a page table for each address space in memory. The page table is constructed by the linear array of the entrance, with the VPN as the index, the format of the VPN is the same as the bit field in the ENTRYLO register. The R3000 type single entry TLB needs to give each of the words of one word, and the R4000 type is the TLB of the R4000 type requires 4 word lengths (each inlet is due to the greater address space).
This design is very simple, but it has brought other problems. Since each 4kb in the user space needs to take up a 4-byte long table space, then 2GB user space requires 2MB table, which is an uneasy huge capacity. Of course, most user address spaces are filled with bottom (code and data) and top (a downward-growing stack), there is a huge gap in the middle. The solution taken by MIPS is inspired by the VAX architecture, that is, put the page table itself in the virtual space of the KSEG2 area. This immediately concluded 2 questions:
n Save physical memory; because the gap that is not used in the middle of the page will never be referenced, there is virtually no physical memory being assigned to those entrances.
This re-maps a new user page table for context to provide a simple mechanism so that there is no need to find enough virtual addresses in the operating system to immediately map all page tables. You just need to change the value of the ASID, then the page pointed to which KSEG2 points to the correct page table is automatically re-mapped to the correct page table. This is simply magic!
Of course, this seems to have caused a fatal vicious circle, and a TLB reloaded into the desired thing (mapping to KSEG2 loaded) requires another TLB reload. We can also solve this problem: n is not all reinstalled in an abnormality that will call the fast TLB re-entry program; a nested TLB of the page table will be sent to a universal exception handling entry point.
n Provides a limited set of mechanisms that allow us to process nested exceptions (kernel TLB not intended) from the user's TLB. We will discuss this in the following: Because the R4x00 and subsequent 64-bit CPUs use small tricks than R2000 and 32-bit CPUs.
The MIPS architecture supports this linear page table by the format of the Context register (or XContext register set by the 64-bit CPU extended address.
If you order the page table to set the Context's PTEBase domain with the high position of the page table start address, then the Context register will hold the entrance address you need to reload as the user's re-installation of exceptions. Don't need more calculations.
6.7.1 32-bit R3000 Types of User TLB is not hired
The 32-bit CPU has an exception handling entry point for handling the TLB of the user to access the address. The TLB could not be delivered to a standard exception processing inlet due to address access restrictions. Here is a typical 32-bit CPU reinforcement procedure:
.set NoreOrder
.set noat
TLBMISSR3K:
MFC0 K1, C0_CONText # (1)
MFC0 K0, C0_EPC # (2)
LW K1, 0 (K1) # (3)
NOP # (4)
MTC0 K1, C0_ENTRYLO # (5)
NOP # (6)
TLBWR # (7)
JR K0 # (8)
RFE # (9)
.set At
.set reorder
UTLB's non-interesting exception is a small piece of very bottom code, so .SET NOREORDER tells the assembler (Assembler) We will have the responsibility of this code sequence in the CPU's pipeline, without the need for assembler to care about this . .SET Noat tells the complaint that does not allow the use of the AT register to integrate instructions - this is important because we are entry from an arbitrary exception, and there is still a user state that is not saved in the AT register.
K0 and K1 are determined to be used for us, so we don't have to worry about our content covered by it.
Here is a progressive analysis of this code:
1) The Context Register is the pointer of the page table. The MFC0 instruction does not immediately generates the 5-level pipeline of MIPS, so we cannot use this pointer before line (3).
2) Something we will need to use the return address; now do this in Delay Slot. This also needs to be done in the case of the TLB missed abnormality in the page table itself.
3) The entrance address of the page table is running to this time may not be legally translated in the TLB. In this case we will generate another anomalies here. We will handle this situation later.
4) Say the instruction requires 2 clock cycles, so we need to wait for it before you can use the value of the page table. 5) Save the new value to ENTRYLO. EntryHi (VPN) is automatically set by hardware when the TLB is not intended, and the value represents a missed address. Entryhi has retained the ASID value of our previously deposited, assuming that the operating system has done a process context.
6) Waiting for a new value to reach Entrylo.
7) Write the content to the current Random register to write content, discard the original value ... Which location it is. But it doesn't matter, this is the interesting thing that is randomly replaced.
8) Return to the user program, but every time the instruction in the delay slot will be executed before we jump to an address ...
9) The RFE instruction is used to restore the CPU status before the exception saved in the SR register.
This way we use 9 instructions and then returns to the programs that have suffered from TLB. The biggest overhead is generated when data is not hired when data is taken from the page table.
But we guarantee that you explain to you if you are not going to run in the page table entry address, there is no translation of the entry in the TLB.
One thing is not a problem: Double translation fails like this is not common, so we don't have to worry about efficiency. The universal exception handling of a heavyweight level is possible for the TLB of the Page Table (in the privileged address space).
MIPS is actually only three things:
n Modify SR to turn off the interrupt and make the CPU to the kernel mode
N Save the restart position in the EPC
n is booted to the abnormal handler
To allow the occurrence of the second abnormality and can be returned to the original program, we need to avoid losing the original return address and can recover SR to become the value of the last abnormality.
No hardware supports saving return addresses, but you can see it above, the exception handler has saved it in K0; we only need to ensure that the universal abnormality handles K0 like most other registers, and protects the value.
The status register is complex, but the hardware here is indeed some support. The two signs of the role are interrupt enable bit SR (IEC) and kernel mode flag bit SR (KUC). The status register actually provides a three-layer stack for these two bits, which is stack in the abnormality generation, while the array is moved when an exception ended, as shown in Figure 6.8.
Because SR (KUX, IEX) built a three-layer stack, even in the second abnormality, the value of the user program is still safe to save in SR (KUO, IEO), ready to be bounce back correctly .
Figure 6.8
6.7.2 R4x00 Type CPU TLB pennaries
The R4000 and the later CPU use the TLB of the entrance, and the conditions for processing double abnormalities have different, which results in this different processing code.
The R4000 has 2 special exception entry points. The entrance to the same position as the R3000 is only used to process translation of 32-bit address space; another entry is supplied to a program that is marked as a 64-bit pointer that can handle greater address space.
The status register of the R4000 has three domains, SR (UX), SR (SX), and SR (KX) to choose which exception handler is selected based on the privileged level at the CPU when the failure translation occurs.
The R4000 has different standards in determining when the TLB is not intended to use a special processing entry and when it is distributes it to a generous exception handler. Unless the R4000 is already dealing with an exception - that is, unless SR (EXL) is placed -, it will always use a special processing entry. When processing dual abnormalities, just as mentioned above; but because the kernel address is not intended to pass the same TLB handler as the user address, the page table of the R4000 must be greatly sufficient to across the kernel (also produced more Big "empty"). Here is the R4000's 32-bit address space TLB pennable processing code:
.set NoreOrder
.set noat
TLBMISSR4K:
DMFC0 K1, C0_CONTEXT # (1)
NOP # (2)
LW K0, 0 (K1) # (3)
LW K1, 8 (K1) # (4)
MTC0 K0, C0_ENTRYLO0 # (5)
MTC0 K1, C0_ENTRYLO1 # (6)
NOP # (7)
TLBWR # (8)
Eret # (9)
.set At
.set reorder
Below is a progressive analysis of the code:
(1) This is a bit blamed, and the 64-bit handling instruction seems to be unsentful: if the page representation is usually like kseg2, then the Context's page cluster site will be ensured in the high level 1, so here if you are here With 32-bit MFC0 instructions, the K1 register obtains the same value.
(2, 7) Certain CPUs (usually the CPU of the pipeline exceed 5 levels, such as R4000) require additional NOP instructions in this location.
(3-6) The entrance here is paired, but EnTrylO0 and EnTrylo1 are still only 32-bit registers. However, the Context register is set for the 16-byte length page entry; the entrylo0 and entrylo1 in these CPUs don't care, the software program requires some page tablespace to keep some information for software for software.
The NOP instruction is not required because we use the second LOAD instruction, so there is always one other instruction between each pair of LOAD and MTC0 instructions to separate them.
Just as before, if the address of the page table inlet does not legally translate in the TLB, we may meet another exception. This time we are still discussing this later.
(7) Here you may need a NOP instruction on some CPUs, you need one on the R4000 of the long flow wire.
(8) Here is the same as previously discussed, is a random replacement.
(9) MIPS III and subsequent CPUs have an eret directive to return from an exception, and restore SR changes due to abnormal (for MIPS III CPUs, all things made by an exception to SR are set up a SR (EXL) bit. ).
In these subsequent CPUs, what happens if there is another TLB missed? As before, the second noisy will be sent to a generic exception handling inlet, but this time is due to SR (EXL) (indicating that an exception is being processed). The resulting results are also different from R3000. Allows the second exception when SR (EXL) is set, but this does not cause the replacement exception return address register EPC.
In the effect, the kernel TLB is not intended to cause control to transfer the universal exception handling entry while setting the Cause register and all the registers for indicating the TLB misset address, but EPC still points to the initial user. Space results in an instruction. The kernel page will not be resolved in the hit (if possible), then universal exception handle will return to the user program. Obviously, we have not done anything to handle the original user address space TLB, so this will immediately produce a missed. However, this time, the desired core translation content is available, and the user's mortal can also be successfully completed.
6.7.3 XTLB misses
By setting the appropriate bit (generally SR (UX)), TLB is not hired to be sent to a different processing vector, where we should have a program for translational loads for large address spaces. The processing code appears to be the same, in addition to using the XContext register instead of Context:
.set NoreOrder
.set noat
TLBMISSR4K:
DMFC0 K1, C0_XCONTEXT # (1)
NOP # (2)
LW K0, 0 (K1) # (3)
LW K1, 8 (K1) # (4)
MTC0 K0, C0_ENTRYLO0 # (5)
MTC0 K1, C0_ENTRYLO1 # (6)
NOP # (7)
TLBWR # (8)
Eret # (9)
.set At
.set reorder
However, please note that the page table structure in the kernel virtual memory obtained is much larger than before, and we need to make some minor changes to the kernel false map and translation code to accommodate this.
6.8 Tracking the modified page (the simulation "dirty" bit)
The operating system for providing the page is often required to track this page since the last operating system acquires it (possibly from the disk or on the network) or saved it after it is saved. The page that is not modified ("Clean") can be discarded directly because they can simply restore them from the file system next time.
In the operating system, those modified pages are called "dirty", and the operating system must pay close attention to them until the application exits or these Dirty pages are saved back to clear. To help implement this process, the CISC CPU usually maintains a bit in the memory resident page table to indicate a write operation on this page. The MIPS CPU does not support this feature and even in the TLB entry. The D bit of the page table is a write allow bit, of course, is also used to log read-only page.
Here is the skill:
n When a writable page is loaded into memory, its D b bit of the entry is not changed (i.e., let it become read-only). n When any one attempts appear to appear on this page, it will generate a fall; system software will identify this is a legitimate write action but set a modified bit in the regular station table in the regular station table - due to it in Entrylo (D The location, this allows the future write operation to be smooth without producing an exception.
n You may want to allow write operations by setting D bits in the TLB page table, but since the TLB entry is randomly and unpredictable, this method is not helpful to remember the modified state.
6.9 Memory Translation and 64-bit pointers
When the MIPS architecture is invented, the 32-bit CPU has a period of time, and the largest program data has reached a 100MB-address space, only 4 digits remains around the left and right can be used to assign. So we must use 32-bit spaces reasonably and to avoid erosion erosion of the fragments they are willing; this is why the app (in user-level running) will preserve 31-bit address space for himself.
When the MIPS III instruction set introduces 64-bit registers in 1991, it is the industry leader, and as we discussed in Section 2.7, the MIPS exceeded 32-bit address restrictions to truly stress about 4 to 6 years. Double register size is only necessary to generate a small amount of additional address bits to accommodate future needs; careful data structures that should be potentially explosive growth to the operating system becomes more important than effective use of all address spaces.
The actual address space caused by basic 64-bit address mapping is still unable to solve within a period of time; they allow the mapped user space or other space to increase to 61-bit address size. However, the XContext (VPN2) domain "only" 27 digits, which limits the mapped user virtual address of 40 bits. How do we implement a 40-digit user space?
A page table with XContext
Entrance (one value of each corresponding R / VPN2, 16 bytes long). That is 8GB space, exceeding KSEG0, KSEG1 and KSEG2 combine the entire space size can be represented. Fortunately, there is another one in R4x00 and subsequent CPUs.
Byte size, kernel level permissions, available from the 0xC000 0000 0000 0000 start-up mapping area. Most of this table is empty because 40-bit user program address space (R = 0) has a very vast gap in the stack and data segment, used in the privileged area Even less. The section associated with this gap in the page table will never be accessed, and do not need to be mapped to physical memory at all. Obviously, use a relatively compact data structure to map the kernel permissions address is useful, but this is involved in the design of the operating system, which exceeds the scope of this book.
6.10 MIPS TLB daily use
If you are using a huge operating system, it will use TLB and you have hardly see it. If not, you may doubt it is useful. Since MIPS TLB provides a relatively universal address translation service, you may benefit from many ways.
The TLB mechanism allows you to convert addresses (on page sizes) to any physical address, which can relocate the program's address space to any address map on your machine. If your mapping needs limited, you can do all translations in TLB, then you don't need to support TLB reissue into an exception or an additional memory resident page table.
TLB also allows you to define some addresses for temporary or permanent unavailability, so access to those addresses will cause an exception to trigger some operating system service programs. By using user-level programs, you can allow some software to access those addresses you want them to access, and by using user address space IDs in those addresses, you can effectively manage multiple user programs that are unacceptable. You can write to protect a part of memory. The application of TLB is not just this, but there is a list here to indicate the range of applications:
n Access Incidential Physical Address Range: Most of the hardware registers of the MIPS system conveniently located 0-512MB ranges of the solid site, you can use the corresponding pointers in the KSEG1 area to access this range. With the address of hardware that is not in this expectation area, you can map its real address to a convenient map area, such as KSEG2. This translated TLB flag should be set to not cache, but the program can be used as the convenient location when writing the program next to the program.
N The memory resource of the exception handler: Suppose you want to save the site when you want to run an exception handler to save the site. In this case, you may encounter trouble, because usually the MIPS CPU does not have to write other at least one register when you save the register. You can use the zero register as the base address to perform the LOAD or Store action, but after a positive offset value (Offset) is located within the first 32KB of Kuseg, and a negative offset will be The last 32KB of KSEG2. These are nothing to use without using TLB. With the TLB, you can map one or more pages of this area or multiple pages to the readable memory area, then use the 0 base address to save the context to save your exception handling.
N-non-dummy systems stretched stacks and stacks: Even when you do not have a disk and not support full paging requirements, it is also useful to expand them based on the growth of the monitoring application's stack and piles. In this case you need TLB to map the address of the stack or heap, then decide whether to assign more memory or applications according to the TLB penalty event.
n Simulated hardware: If you have some of the hardware that is not available to some time, you can access its register through the mapping area to access its registers directly to the hardware, and access to unavailable hardware Call the abnormality processing of a software.
All in all, there are all of these exquisitely designed TLBs that comply with large operating system specifications, is a very useful and can directly facilitate the general resources of the programmer.
6.11 Memory Management of Non-Unix Operating Systems
The operating system designed to be used outside the desktop is generally referred to as a real-time operating system (RTOS), which has been used to represent some real-time terms. The first part listed The UNIX class operating system has the elements you can find in the small operating system, but many RTOS will be more concise.
This field is very new and there is no factual standard. Pioneers in the field may be Microsoft's Windows / CE, and the internal description of the operating system is currently not free to get. So we will limit the topic within a few aspects.
Non-desktop systems are more inclined to provide a simple and tightly integrated function method; do not need to support a large-scale program, including third-party or user-written programs, and the processes are not particularly important. We expect smaller operating systems to have more operations, which is because the application's writer influence is stronger. This is not very good to do so, but the earlier RTOS has no protection mechanism.
As a way of loading procedures, the tag is very meaningful, because you don't need to do the job of the part of the program that doesn't need. The system without a disk may not change the page containing Dirty data, however, the page is still useful without it.
