The MAKE program was originally designed to maintain the C program file to prevent unnecessary recompilation. When using the command line compiler, modify the header file in an engineering, how to ensure that all files containing this header are compiled? Now the 10-machine version generation is a batch program, compiling those files depending on the programs, with each other, the module references the header file, to find all the files that need to be recompiled to find a painful thing. After finding these files, modify the batch is compiled. In fact, these work can be made automatically, and the Make tool is especially useful for maintaining some files with mutual dependencies. It provides a set of encodes for files and commands. method. The basic concept of the Make tool is similar to the Proglog language. You tell Make what you need to do, provide some rules, make to complete the rest of your work.
1 Introduction Make work automatically determines which part of the project needs to recompile, execute the command to compile them. Although Make is used for C procedures, as long as you provide a compiler of the command line, you can use it for any language. In fact, the Application range of the make tool is not only programmed, but you can describe the tasks that need to be automatically updated to other files to use it.
1.1 Preparation If you want to use Make, you must write a file called "makefile", this file describes the relationship between the files in the project, providing the command to update each file. Typical projects are like this: executable files reimcomulate the target file, and the target file is updated by compiling the source file. After Makefile is written, each time you change the source file, you will be enough, and all necessary recompilation will be executed. The Make program uses the last modification time of the database and file in Makefile to determine that the file needs to be updated; for updated files, Make executes the command recorded in the database. You can provide command line parameters to make Make to control that file needs to be recompiled.
1.2makefile Introduction Makefile file tells make what is doing, how many cases are compiled and linked. Here is a simple Makefile, describing how to compile links consisting of 8 C files and 3 head files: Edit: main.o kbd.o command.o display.o insert.o serach.o files.o utils .occ -o edit main.o kbd.o command.o display.o utils.omain.o: main.c defs.h cc -c main.ckdb.o: kbd.c Defs.h command.h cc -c kbd.ccommand.o: command.c defs.h command.h cc -c command.cdisplay.o: display.c defs.h buffer.h cc -c display.cinsert.o : Insert.c defs.h buffer.h cc -c insert.csearch.O: search.c defs.h buffer.h cc -c search.cfiles.o: files.c defs.h buffer.h command.h cc -c files.cutils.o: utils.c defs.h cc -c utils.cclean: rm edit main.o kbd.o command.o display.o insert.o search.o files.o utils.o will travel Easy to read with / separate, this is the same as using a long line. Running Make when using this makefile "Edit"; if you want to delete the executable and destination file, execute make cleanmake to recompile this editor, each changed C file must be recompiled; if head The file changes, each C file containing the header file must be recompiled; each compiling a target file corresponding to the original file. Finally, the target file link together generates a new executable. 1.3 Rule Profile The rule in the Makefile is this: target ...: dependencies ... Command ... Targets generated files, such as executable files and destination files; goals can also be active, such as "Clean". Dependencies is used to generate an input file, one goal usually depends on multiple files. Command (Command) is the action of Make, one can have multiple commands, each accounting. Note: The starting characters of each command line must be Tab characters! Commands in the dependency rules typically be responsible for generating Target files while relying on file changes, Make executes these commands to update or generate Targets. Rules can have no dependencies, such as rules that contain Target "Clean". Rule explains how to re-do files in this rule, Make performs or updates the target according to the dependency; the rules also explain how to perform actions. Some rules look complicated, but they all meet the above modes.
1.4make Working principle The default Make starts from the first Target (the first non-'.' Starting Target), this is called the default goal. In the above Makefile, the default goal is to update the execution program 'edit' and place this target at the forefront. When Make is executed, the Make program reads the makefile from the current directory to the first rule; in the example, this rule is resin 'edit'; before the Make handles this rule, the 'Edit' relies on those depends. The rules of the file are the target files. These files are handled according to their own rules: update each '.o' file by compiling the source file; the source file or header file in the dependency is more than the target file, or when the target file does not exist, it must be recompiled. Other rules are processed because their target is the dependence of the target, and the rules that do not depend on the relationship will not be processed unless the MAKE process is specified (such as Make Clean). Before recompiling the target file, make attempts to update its dependencies: source files and header files. The Makefile in the example does not specify any operations in the source file and header file: '. C' and '.h' files are not the goal of any rule. After confirming that all target files are the update, make decides whether to re-link 'edit': If 'Edit' does not exist, or any target file is more new, the link work will be done. This way, if we change the INSERT.C running make, make will compile this file to update 'INSERT.O', then link 'edit'; if you modify 'COMMAND.O' Run Make, 'Kbd.o', 'Command. O ',' files.o 'will regenerate, link' edit '.
1.5 Using the variable in the example, in the rule 'edit', the target file is listed twice: Edit: main.o kbd.o command.o display.o / insert.o search.o files.o utils.occ - o Edit main.o kbd.o command.o display.o / insert.o search.o files.o utils.o This repetition error: Assumptioning a new target file is added, you may only join it. In a list; this risk can be eliminated by using variables: variables allow a predefined string to be replaced in multiple places. In Makefile, you can write such a row to define 'object' variables: objects = main.o kbd.o command.o display.o / insert.o search.o files.o utils.o is then the list of target file names Place, use $ (object) instead of the value of the variable. The following is Makefile after using variables: Objects = main.o kbd.o command.o display.o Utils.OEDit: $ (Objects) CC -O Edit $ (Objects) Main .o: main.c defs.hcc -c main.ckbd.o: kbd.c Defs.h command.hcc -c kbd.ccommand.o: command.c defs.h command.hcc -c command.cdisplay.o o : display.c defs.h buffer.hcc -c display.cinsert.o: insert.c defs.h buffer.hcc -c insert.csearch.o: search.c defs.h buffer.hcc -c search.cfiles. o: files.c defs.h buffer.h command.hcc -c files.cutils.o: utils.c defs.hcc -c utils.cclean: RM Edit $ (Objects) 1.6 Simplified commands write compilation for each file The command is not necessary, because Make can do it yourself; with the '.c' file update '.o' file has an implicit rule, use the 'cc -c' command. Make will use 'cc -c main.c -o main.o' to compile main.c as main.o, so in the rules of the target file, the command can be omitted. When '.c' files are used in such a way, it will be automatically added to the dependencies; the '.c' file can be omitted from the dependency of the dependency. The following is a simplified Makefile: Objects = main.o kbd.o command.o display.o / insert.o search.o files.o utils.OEdit: $ (Objects) cc -o edit $ (Objects)
Main.hkbd.o: defs.h command.hcommand.o: Defs.h command.hdisplay.o: defs.h buffer.hinsert.o: defs.h buffer.hsearch.o: defs.h buffer .hfiles.o: Defs.h buffer.h command.hutils.o: defs.h.phony: Cleanclean: -rm Edit $ (Objects)
1.7 Another style If the goal in Makefile is generated by implicit rules, the rules can be packetized according to the dependency: Objects = main.o kbd.o command.o display.o / insert.o search.o files.o Utils.OEDIT: $ (Objects) cc -o edit $ (Objects)
$ (Objects): Defs.hkbd.o command.o files.o: command.hdisplay.o insert.o search.o files.o: buffer.h here 'defs.h' as the dependence of all target files. This style is good, depending on the personal preference, it is very compact, but puts the dependency information of each goal looks more clearly.
1.8 Cleanup Writing Rules is not compiled. Makefile usually describes how to do other things: such as deleting target files and executables in the directory to clean up directories. In the example: Clean: RM Edit $ (Objects) The actual situation is that we need to handle some accidents: there is a file called 'clean'; if the RM is wrong, it does not want the Make process to stop, modified The version is as follows: .phony: Cleanclean: -rm Edit $ (Objects) This rule cannot be placed in the beginning of Makefile, because this is not our default job. Since 'Clean' is not 'Edit''s dependencies, this rule will not be executed when there is no parameter when running Make; to perform this rule, you must run 'make clean.
2 MakeFilemakefile includes five contents: explicit rules, implicit rules, variable definitions, instructions (Directive) and comments. • Explicit rules describe how to generate rules, which lists the target-dependent files, specify commands to generate or update the target? And the file named its file name specified the corresponding command. • Directive Similar to the directive of the compiler, including:?; Indicate Make reads another makefile ?; Decide whether to ignore some of the Makefile?; Define a variable?; A line '#' starts to comment until the end of the line, Unless the continuation symbol is encountered. In 'Define' and commands cannot be annotated, the comments can appear anywhere in other cases.
2.1makefile Name Default, Make The following name looks for Makefile: 'gnumakefile', 'makefile' and 'makefile' (accountation). Usually your makefile should be called 'makefile' or 'makefile'. 'Gnumakefile' does not recommend unless your makefile is customized for the GNU Make, other make does not think that the name is an Makefile name. If you use a non-standard named makefile, you must use the command switch '-f' or '-file'. The parameter '-f name' or '-file name' tells make reads Name as Makefile. If multiple switches are used, all files will be connected in sequence. If you use this option, the standard Makefile name will not detect.
2.2 Contains 'Include' instructions Tell MAKE to pause the rest of the content and read other makefiles. The syntax is as follows: Include filenames ... This line can have spaces, but Tab characters are not allowed. If the file name contains variables or functions, these will be extended.
2.3'makefile 'Variable If the environment variable' makefile 'is defined, Make thinks that its value is a series of spaces separated by the Make program before processing other makefiles. This is similar to the include directive; the targets in these files do not affect the default target, and if the file is not found, make does not think it is wrong. The main purpose of this variable is to recurs the reference Make program. Transmission 2.4 How to regenerate Makefile Sometimes makefile is generated from other files, such as RCS or SCCS files. If Makefile is generated by other files, you need Make to read the latest version of Makefile. After reading all makefile, make thinks each makefile is a target, trying to update it; if there is a how to update its rules in Makefile, or have an applicable implicit rule. After all Makefile check, if there is any change, make again restart (Make will try to do updates, but usually will not change again, because it is already the latest). If a file uses a double-cut number rule, it provides commands but no dependencies, and the file will always be updated. In the case of Makefile, if the Makefile dual-colon rule provides commands but no dependencies, Makefile always regenerates, which will cause the loop: make just update Makefile, but does not work. To avoid this, Make will not regenerate Makefile that only commands that there is no dependency that does not depend on relationship. If you do not use the '-f' or '-file' option, Make will try the default Makefile file name. Unlike the point of the '-f' or '--file' option, Make cannot determine if these files should exist. However, if the default Makefile does not exist but can be generated by running the Make rule, you may want these rules to be run so that Makefile can be used. Therefore, if there is no default Makefile, make attempts to generate it in the order in which the Makefile name is found, until success or name is used. Note that if Make can't find or generate makefile, this is not an error; makefile is not always necessary. When using the '-T' or '--tonch' option, you don't want to use the time-time Makefile to determine the target to touch. So the '-t' option does not work on the Makefile update; "or '-question') and '-n' (or '-just-print') does not block Makefile updates because the Oversers of Makefile will Generate an error output. Such 'Make -f mfile -n foo' updates 'mfile', read it, prints the command that updates 'foo' needs to be executed but does not run these commands. The command related to 'foo' is the content of the updated 'mfile'. However, sometimes you don't want to update your makefile, you can use your makefile as the target line. When Makefile is explicitly specified as a target, the '- t' option is also available for them. Such 'Make -f Mfile -N Mfile Foo' reads 'mfile', prints the updated command, 'foo' command is the content in the current 'mfile'.
2.5 Overload Makefile You can use the 'include' instruction to include other Makefile, add the target's variable definition. However, Make does not allow the same target to have different commands, and other ways can achieve the purpose. There is a 'Makefile' and 'mfile', 'Makfile' to include 'mfile', but there are rules for target 'foo'. This is a rule that can be written in 'Makefile', indicating that Make is not found in 'makefile', searching 'mfile': foo: frobnicate> foo%: Force @ $ (Make) -f mfile $ @ force:; When performing 'make foo', Make finds 'Makefile', executes 'frobnicate> foo'; when performing 'make bar', the corresponding rule is not found in 'makefile', when the mode rule applies Other objectives not mentioned in 'make -f mfile bar', 'makefile' are also true. The reason for this method is because the mode rule mode is '%', which can match any target; dependence on this rule is 'Force', ensuring that even if there is a command, the command of the 'Force' rule is empty Prevent 'Make' from searching for implicit rules - this will result in dependency loops. 3 Rules Makefile The rules of Makefile describes how to generate a specific file, ie the target of the rule. Rules lists the destination files, specify commands to generate or update the target. The order of the rules is not important unless it is determined that the default goal: the default goal is the first rule in the first Makefile; if the first rule has multiple targets, the first goal is default. There are two exceptions: Targets beginning with '.' Are not the default goal; the mode rules have no effect on the default goal. Usually one rule we have written is to compile all the programs specified throughout or makefile.
3.1 example foo.O: foo.c defs.h # module for twiddling the frobscc -c -g foo.c It is 'foo.o', depending on 'foo.c' and 'defs.h', there is A command 'cc -c -g foo.c'. The command line identifies it as a tab character. It is a command. This rule illustrates two things:?; How to determine 'foo.o' is old: If it does not exist, or 'foo.c' or 'defs.h' is newer than it. ? How to update the 'foo.o' file: By running the 'CC' program. The command did not mention 'Defs.h', and the responsibility can guess 'foo.c' contains it, this is the reason for 'DEFS.H' is placed in the dependencies.
3.2 The syntax syntax of the rules is as follows: targets: dependenciescommand ... or targets: dependencies; CommandCommand ... targets is a file name spaced from a space, and the unmanagers can be used. Usually one rule has only one goal, occasionally there are multiple. The command line begins with the Tab key. The first command can be the next line of dependencies; or in the same line, behind the semicolon; the same effect is the same. Because '$' symbols are used to use variable references, if you want to use '$' symbols in rules, you must write two: '$$'. You can use '/' symbols to split a long row, which is not necessary because Make is not limited to the length of the line.
3.3 The file name in the wildcard rule can contain a uniform, such as '*', '?'. The character '~' in front of the file name has a special meaning. Use alone, or follow one '/', represent the user's Home directory, such as' ~ / bin 'extension to / home / you / bin'; if '~' follows a word, represent the user's Home directory of the word indicated by the word. Such as '~ john / bin' extension is '/ home / john / bin'. Wildcards are automatically extended in target, dependencies, and commands, in other cases, unless explicitly use 'Wildcard' functions. The special meaning of wildcards can be shut down using '/' symbol. Example: Clean: RM -F * .O and print: * .c lpr -p $? Touch Print WWER does not expand when defining variables, for example: Objects = * .o, the value of Objects is string '* .o '; But if you use Objects to target, dependency, or commands, the extension will be performed. To set Objects to extended content, use: Objects: = $ (Wildcard * .o) 3.3.1 Wildcard Defects This is an example using wildcard, but the result is not what you expect. Suppose the executable 'foo' is generated from all '.o' files from the current directory: Objects = * .o
Foo: $ (Objects) CC -O Foo $ (CFLAGS) $ (Objects) Objects Variable The value of the string '* .o'. Wildcard extensions are performed in rule 'foo', so all existing '.o' files are dependence on 'foo' and recompile when needed. But if you delete all the '.o' files? When the wildcard does not match any file, everything is maintained: 'foo' depends on a file called '* .o'; because this file is unlikely, the 'make' program will report a unable to generate '* .o 'The error of the file, this is not the result of the expected. It is actually possible to obtain a desired result with wildcard, but complex technologies, including the 'Wildcard' function and string replacement function.
3.3.2Wildcard function wildcard automatically performs in rules. However, the wildcard does not extends in the parameters of the variable assignment and the function, and if a wildcard extension is required in these cases, the 'wildcard' function must be used. The syntax is as follows: $ (Wildcard Pattern ...) This string appears anywhere in the makefile, replaced with an existing file list that is spaced apart in any file name format. If no file matches a mode, this mode is ignored from the 'Wildcard' output, note that this is not the same as the above-described wildcard. A function of the 'WildCard' function is to find all the '.c' files in the directory: $ (wildcard * .c) can get a list of destination files from the C file list by replacing the suffix '.c' to '.o' list: $ (PATSUBST%. C,%. O, $ (Wildcard * .c)), Makefile rewritten in the last section is: Objects: = $ (PatSubst% .c,%. O, $ (Wildcard * .c) )
Foo: $ (Objects) CC -O Foo $ (Objects) This makefile uses the implied rules of compiling C programs, so it is not necessary to write explicit rules to compile. (': =' Is a variant of '=') Note: 'Pattern' is sensitive.
3.4 Directory Search For large systems, the source files and target files are usually placed in different directories. Directory Search feature allows Make to automatically search for dependencies in multiple directories, when you resemble files, do not need to change the rules, change the search path. 3.4.1'vpath'mke Variable 'vpath' Lists the list of Make should search. In many cases, the current directory does not contain dependencies, 'vPath' describes a list of search lists for all files, which contains files that are rules. If a goal or dependent file is not found in the current directory, the files listed in the directory listed in 'vpath' in 'vPath'. If you find it, that file is a dependency file; the rule can use them like these files in the current directory. In 'vPath' variables, the directory name is separated by colon or spaces; the order in which the directory is listed determines the order of the Make. (Note: The GNU Make directory name transplanted to Win32 in PSOSYSTEM 2.5 must be separated by semicolons, and the following is referred to as Win32 GNU Make). for example:
Vpath = src: ../ Headers rule foo.O: foo.c is interpreted as foo.o: src / foo.c hypothesis 'foo.c' does not exist in the current directory, can be found in the 'src' directory.
3.4.2 Selective Search is similar to the 'vPath' variable but more selective is the 'vPath' instruction (note is lowercase), which can specify a lookup path that conforms to a specific mode file. This can specify different search paths for different types of files. The 'vPath' instruction has three forms:?; 'vPath Pattern Directories' Specifies the search path Directories, directory separation and 'vpath' of the file name and 'vPath Pattern' to match the file name of the matching Pattern. Search path?; 'VPath' Clear all previously used search path 'vpath' mode is a string containing '%' ': this string must match the dependency file name that you need to search,'% 'characters match 0 or more arbitrary characters. For example: '%. H' matches any file ending with '.h' (if not%, Pattern must be completely consistent with dependencies, this usage is not much). When there is no dependency file in the current directory, if the Pattern matching dependent file name in 'vPath', the directory listed in the directory and the 'vPath' are also processed. Example: vpath% .h ../headers Tell Make's '.h' file in the current directory in ../headers directory. If multiple 'VAPTH' mode matching dependencies, make will proceed one by one, search in all specified directories. Make In accordance with the order of 'VAPTH' in Makefile; to process them, the 'VAPTH' of multiple identical modes is independent of each other. vpath% .c foovpath% blishvpath%. C Bar will find '.c' files in the order of 'foo', 'blish', 'bar'. VPATH% .c foo: barvpath% blish searches in the order of 'foo', 'bar', 'blish'.
3.4.3 The result of the search using the automatic variable directory does not change the command in the rule: The command is executed as it is. Therefore, you must write a command that is adapted to the directory search work. This can be done by using the automatic variables such as '$ ^'. '$ ^' Represents all dependencies in the rules, contains their directory name (see directory search); '$ @' represents the target. For example: foo.o: foo.ccc -c $ (cflags) $ ^ -o $ @ ^ Usually, dependent files also contain header files, but do not mention these files in the command: Variable '$ <' represents the first Dependent file: vpath = src: ../ Headersfoo.o: foo.c defs.h Hack.hcc -c $ (cflags) $ @@3.4.4 directory search and implicit rules use 'vpath' and 'vpath' specifies directory search also affects implicit rules. For example: file 'foo.o' has no explicit rules, makers will consider implicit rules: If the 'foo.c' exists, it compiles it; if this file does not exist, look for the corresponding directory; if 'foo.c 'In either directory, the implicit rules of C-compilation are applied. The command of the implicit rule is usually necessary to use auto variables, so you can use the file name to get in the directory search without other efforts.
3.5PHONY Target PHONY target is not actual file name: just execute the name of the command when explicitly requested. There are two reasons to use PHONY objectives: avoiding conflicts with the same name file, improve performance. If a rule is written, does not generate a target file, its command is performed at each MAKE target. For example: Clean: rm * .o Temp Because the 'rm' command does not generate 'Clean' file, the command will execute each time 'make clean'. If the 'Clean' file appears in the directory, the rules have been invalidated: no dependencies, file 'clean' is always the latest, the command will never be executed; to avoid this problem, you can use '.phony' to specify this goal. Such as: .phony: Clean This executes 'make clean' will ignore the 'Clean' file or not. It is known that the PHONY target is not actual file generated by other files, and Make will skip the implicit rule search. This is why the PHONY target will improve performance, even if you don't worry about the actual file. Complete examples are as follows: .phony: Cleanclean: rm * .o Tempphony target does not be the dependence of true destination files. If so, each MAKE is updated when this file is updated, the command will execute. As long as the PHONY target is not the real target, the rule's command is only executed when this goal is specified. The PHONY target can have dependencies. When there are multiple programs in a directory, it is more convenient to put it in a Makefile. Because the default goal is the first target in Makefile, this Phony target is usually called 'all', its dependent files are all programs: all: prog1 prog2 prog3.phony: Allprog1: prog1.o utils.o cc -o prog1 PROG1.O Utils.oprog2: prog2.o cc -o prog2 prog2.oprog3: prog3.o sort.o utils.o cc -o prog3 prog3.o utils.o, using 'make' will be able to The program is generated. When a Phony target is another dependence, its role is equivalent to a subroutine, for example: .phony: CleanAll Cleanobj CleanDiff RM Programcleanobj: rm * .ocleandiff: rm * .diff3.6force target When the rule does not depend on the relationship Command, and its goal is not the existing file name, make this target is always updated when this rule is runtime. This means that if the rule relies on this goal, its command is always executed. Clean: Force RM $ (Objects) Force: Example The target 'force' met this special condition, which relies on its target 'clean' being forced to execute its command. Name 'Force' does not have a special meaning, but it is usually used. This way is the same as 'force' and '.phony: Clean' effect. Use '.phony' more clear and efficient, not all 'make' support; so many makefiles use 'force'.
3.7 Empty Target is a variety of PHONY targets: an action used to perform explicit requests. Unlike the PHONY objective: This goal file can be true, the content of the paid file is irrelevant, usually empty. The purpose of the empty target file is to use its last modification time to record the time of the last execution of the command, which is achieved by updating the target file using the 'touch' command. Print: foo.c bar.c lpr -p $? Touch Print Use this rule to perform 'make print', if you change the file since the last 'make print', the 'lpr' command will execute. Automatic variable '$?' Is to print only those changing files. 3.8 Built-in Special Target Some names have special meanings as the target. ★ .phony's dependency is considered to be a phony target, when processing these goals, the command unconditional is executed, regardless of whether the file name exists and its last modification time ★ .suffixes dependent is considered a suffix list, check the suffix When using ★. DEFAULT, the rules of this target are used on the target without rules (explicit or implicit). If the 'default' command is defined, the group command will be executed for all dependencies that are not rule destinations ★ .precious's dependent file will be specially treated: if Make is suspended by the kill or command, these goals are not Delete; and if the goal is an intermediate file, it will not be deleted when it is not required. You can use the target mode of the implicit rule (such as% .o) as a '.precious' dependent file, which can save the intermediate file generated by these rules. ★. Intermediate This target's dependencies are treated as an intermediate file; if the target does not rely on files, all target files in makefile are considered an intermediate file. ★. Ignore When executing the rule of the rule of the target, make ignores errors, this rule itself is meaningless. If the rule does not depend on the relationship, it means that the error is ignored by all commands, which is just backward compatible; because it affects all commands, it is not particularly useful, and the other more selective ignore errors are recommended. ★ .silent When executing the rule of the rule of this goal, make does not print the command itself. The order of this rule is meaningless. When '.silient' does not rely on relationship, it means that all commands in executing Makefile will not print, which is only provided backwards. ★ .Export_all_variables is only existing as a target, indicating that Make outputs all variables into the child process. When the suffix of the defined implicit rules is also considered to be a special goal; the two suffixes are also the same, such as '.c.o'. These goals are suffix rules, define an obsolete method for implicit rules (but still widely used). The suffix is usually start with '.', So special goals are also starting with '.'.
3.9 A number of rules have multiple targets and write multiple rules, each one of the targets is equivalent. The same command is applied to all goals, but its utility will differ from the actual target instead of '$ @'. The dependencies of all targets in the rules are the same. This is useful in both cases: ★ Only dependence, no commands are required. For example: kbd.o command.o files.o: command.h ★ All targets are the same. The command does not need to be identical, because '$ @': Bigoutput LittleOutput: text.g generate text.g - $ (Subst Output, $ @)> $ @ and bigoutput: text.g generate text.g -big> BigoutPutlittleOutput: text.g generate text.g -little> LittleOutput is equivalent. Here you hypothesize that the program 'generate' generates two outputs: a use '-big' option, a '-little' option. If you want to change dependencies as the '$ @' change command, you cannot achieve a multi-objective normal rule, but you can implement it through a mode rule. 3.10 A multi-rule a file can be a target of multiple rules, and the dependencies of all rules are merged. If the target is older than any one dependent file, the command is executed. A file can only have a set of commands. If multiple rules give commands for the same file, make use the last group and print error information (special case: If the file name is "right, do not print the error message, this is to compatible with other make ). There is no reason to write makefile to this, this is the reason for Make gives an error message. A additional rule that only rely on relationship can give additional dependencies for many files at a time. For example, 'Objects' variables represent all outputs of the compiler in the system. Description All files must be done when all files are changed when 'config.h' changes are as follows: Objects = foo.o bar.ofoo.O: Defs.hbar.o : Defs.h test.h $ (objects): config.h does not have to change the rules generated by the actual target file, which can be inserted or proposed when you need to add additional dependencies. Another trick is that additional dependencies can be represented by variables. When Make is executed, the variable can be assigned: EXTRADEPS = $ (Objects): $ (extradeps) When the command `make extradeps = foo.h 'is executed,' foo .h 'is the dependent file of each target file, but the simple' make 'command is not the case.
3.11 Static Pattern Rules Static Pattern Rules can specify multiple targets, and use the target name to rely on the name of the file; more common than ordinary multi-target rules because it does not require the dependency relationship: dependency must be similar There is no need.
3.11.1 Syntax Targets ...: target-pattern: Dep-patterns ... Commands ... Targets list points to the target of the rule application, which can contain wildcards, the same as the target of ordinary rules. Target-pattern and dep-patterns indicate how the target's dependency is calculated: Match Target-Pattern's goals take a part from the name, called the word dry (STEM), the stem is replaced to the DEP-PATTERNS to form a dependent file name. Each mode usually contains a '%' character. When target-pattern matches a target, '%' characters can match any part of the target name; this part is the word dry, the rest of the mode must be fully matched. For example, 'foo.o' matches '% .o', 'foo' is the word dry; target 'foo.c' and 'foo.out' do not match this mode. The dependency file name of the target is replaced by the '%' in the DEP-PATTERNS to form dry: If the dependency mode is '% .c', the word dry 'foo' can get 'foo.c'. The dependency mode does not include '%' is also legal, which is valid for all the goals. If you need to use '%' characters in the mode rule, you must add '/' characters in front, if '%' '' ': the actual meaning, you must add' / ', other' / 'Don't do so. If 'THE /% weird //% pattern //' is 'the% weird /' before paying '%', then 'Pattern //'. The last '//' keeps the same because it does not affect the '%' character. The following example compiles 'foo.o' and 'bar.o': Objects = foo.o bar.o $ (objects):% .O:% .c $ (cc) -c $ (Cflags) $ <-O $ @ Each goal must match the target mode, give a warning for mismatched targets. If there is only some file matching mode in the list, you can use the Filter function to remove the mismatched file name: files = foo.elc bar.o lose.o $ (file% .o, $ (files)):% .o:% .c $ (cc) -c $ (cflags) $ <@ $ (file% .elc, $ (files):% .elc:% .el emacs -f batch-byte-compile $
3.11.2 Static mode rules and implicit rules Static mode rules and implicit rules have a lot of common as a pattern rule, and have a mode of target mode and constructive dependencies. The difference is that Make decides when to apply rules. method. Implicit rules can be applied to any target of matching its mode, but only for the target of the specified command, if there are multiple applicable implicit rules, only one is used, depending on the order of the rules. Conversely, static mode rules apply to the rules to clarify the target list, not suitable for other objects and always apply to each target specified. If there are two conflict rules, and there is a command, this is an error. Static mode rules are superior to implicit rules as follows: ★ Can be categorized for some syntax, but can explicitly listed file overload implicit rules ★ Can't decide the exact content in the directory, some unrelated files may cause MAKE Applicable implicit rules; the final result may depend on the order of implicit rules. This uncertainty does not exist when applicable to the static mode rule: the rule applies to explicitly designated goals. 3.12 Double-colon rules Double-colon rule is the target of '::' instead of ':', when a goal occurs in multiple rules, the processing of its processing and normal rules is different. When a goal occurs in multiple rules, all rules must be the same type: all ordinary or double-selling. If it is a double colon, the rules are independent; if the target needs to be updated, the rule command is executed; the result may not be executed, or some, or all rules are executed. The same goal is completely isolated, and each rule is handled separately, just like the rules of different targets; the rules are processed in accordance with the order in Makefile, and such rules really meaningful are those that are those Not related to the order of execution. This rule is sometimes more embarrassing; it provides a mechanism: Different deals with the target through different relying on files, this situation is rare. Each such rule should provide commands, if not, applicable implicit rules will be used.
3.13 Automatic Generation Dependencies In Makefile, many rules are some target files depend on some headers. For example: 'main.c' uses 'DEFS.H' via '#include', so the rule: main.o: Defs.h tells make to update 'main.o' when 'Defs.h' changes. When the program is relatively large, it is necessary to write a lot of such rules; and when the '#include' each time, you must be careful to update your Makefile. Many modern compilers can help you write these rules, usually this is the '-m' option of the compiler, such as command: cc -m main.c output the following: main.o: main.c defs.h There is no need to write these rules, there is a compiler. Note that this dependency is mentioned in 'main.o', which is not considered an intermediate file, which means that this make will not delete it after use. When using the old 'Make' program, the customary practice is to use the 'make office' command to use the compiler's function to generate a dependency, which generates a 'Depend' file contains all automatically generated dependencies, then use 'in Makefile' INCLUDE 'reads it. When using the GNU's Make, regenerate the functionality of Makefile makes this approach: never need to explicitly request update dependencies because it always regenerates any Out-of-time Makefile. Automatic dependency generating recommendation is a Makefile for each source file. For each source file 'name.c', there is a makefile 'name.d', which lists all files dependent on the target file 'name.o', so when the source file is updated, you need to scan to generate new dependencies. relationship. The example is a mode rule from 'Name.c' to depends on file 'name.d':%. D:% .c $ (shell) -ec '$ (cc) -m $ (cppflags) $ $ @' - E option is when the $ (cc) command fails (Exit Status Non 0), the shell immediately exited. Usually the return value of the shell is the return value of the last command (SED) in the pipe, so Make will not notice the compiler error. When using the GNU's C compiler (GCC), you can use the '-MM' option instead of the '-m' option, so that the dependency of the system header file is omitted. The purpose of the 'sed' command is to convert main.o: main.c defs.h to main.o main.d: main.c defs.h makes each '.d' file dependent on '.o' file Source files and header files, Make can update dependency files when changing in the original or header file. If a rule that generates '.d' file is defined, you can read all files using the 'include' instruction: Sources = foo.c bar.cnclude $ (Sources: .c = .d) uses the replacement variable to The source file list 'foo.c bar.c' is converted to a list of dependency files. Because '.d' files are the same as other files, there is no need to work, and make will regenerate them when needed.
4 The command to write a command rule is composed of one executed shell command. In addition to the commands after relying on a semicolon, each command line must appear in the command line in the command line, and it is ignored when the TAB character is started, and it is ignored (note: the space line starting with TAB characters is not 'Empty' line, is an empty command). You can use any programs in the command, but these programs are performed by $ (shell). 4.1 Events Usually Make prints out the command to be executed, called echo, which is the same as the phenomenon of personally knocking the command. When there is a '@' character before the line, the command is no longer returned, the character '@' is passed to the shell. Typical usage is to valid only for print commands, such as 'echo' command: @echo itt to make distribution file When Make uses '-n' or '-just-print' option, display everything to happen, but does not execute commands . Only in this case, even if the command starts with '@', the command line is still displayed. This option is useful for viewing the actual action to be executed by Make. The '-s' or '-silent' option blocks all the returns of Make, just like all commands start with '@'; a '.silent' rule without relying on relationship has the same role, but '@' is more flexible.
4.2 Do Make when you need to execute the command update target, make each line to create a child shell. This means that the shell command 'CD' (Current Directory of the Process) (the current directory of the process) is not affected by the subsequent command. If you need 'cd' to affect the next command, put them on a row with a semicolon, so Make think is a command to pass to the shell program (note: this requires shell support): foo: bar / lose cd bar; gobble LOSE> ../foo another Using Continued characters: foo: bar / lose cd bar; / gobble LOSE> ../fooshell program's name is made through the 'shell' variable. (* UNIX) is not like most variables, 'shell' variables are not set by the environment (ie, set in Makefile), because the 'shell' environment is a personal selection, if the choice of different people will affect the function of Makefile This is very bad.
4.3 Parallel Executive GNU Make can perform several commands at once. Usually make an command at a time, waiting to return, and then execute the next one. Use '-j' or '-JOBS' to perform multiple commands at the same time. If '-J' is a positive number, it indicates that the number of commands that can be executed; if there is no parameters after '-j', the number of executable commands is not limited. The quantity of the default is one. An annoying question is if the output will be mixed if multiple commands are executed, and the other problem is that the two processes cannot be entered from the same device.
4.4 Errors Each shell command returns, make the make check. If the command is executed, the next command is executed, and the last command is executed, the rule executes the end. If there is an error (return non-0 status), Make gives up the current rules or all rules. Sometimes the command execution error is not a problem, such as using the 'mkdir' command to ensure that the directory exists, 'mkdir' reports an error, but still wants Make to continue. To ignore the error of the command, use '-' character, '-' characters before the command is passed to the shell: clean: -rm -f * .o If you use '-i' or '-ignore-ErrorS' option Make will ignore errors generated by all commands; a '.ignore' rule without relying on relationships has the same role, but '-' is more flexible. When ignoring the error, Make will also think that the error is also successful, just inform you that the exit status of the command and the error are ignored. If Make is not inform ignoring an error, when the error occurs, the target cannot be successfully updated, directly or indirectly dependent on this target is certainly unsuccessful; the commands of these goals will not be executed because they are not satisfied. Usually make immediately exit in a non-0 state. However, if a given '-k' or '-keep-going' option, Make handles other dependencies before exiting, making the necessary updates. For example, in compiling a target file encountered an error, 'make -k' continues to compile other target files. It usually believes that your purpose is to update the specified target. When Make knows this is impossible, it will immediately report failed; '- k' option indicates more possibility of test update: find more before compiling Not related issues. If the command fails, it is assumed that it updates the target file, this file is incomplete - at least not fully updated. But the final modification time of the file indicates that the stop is already the latest, and the next Make is running, this file will not be updated again. This situation and commands are the same as KILL;, it is usually true that the target delete is correct when the command fails; when '.delete_on_error' is the target, Make helps you do this. Although you always want Make to do this, this is not the habit of the past; so you must explicitly ask Make to do this (other make automatically). 4.5 Interrupt Make If an error is encountered when the Make executes a command, the target file that may be updated: make Check the modification time of the file changes. The purpose of deleting the target is to make sure that Make will regenerate it next time. Why did you do this? Assume that the 'ctrl-c' is pressed when the compiler is running, and the compiler is written to generate the target file 'foo.o'. 'Ctrl-c' kill compiler, leave an incomplete file, but its modification time than source file 'foo.c' new; this time Make is also subject to the 'ctrl-c' signal to delete this incomplete file If Make does not do this, the next time Make is considered to be 'foo.o' does not need to be updated, a strange mistake occurs when the link is linked. You can use the '.precious' rule to prevent the target file from being deleted. When the Make update target, it is detected whether it is '.precious', deciding whether to delete the target when the command is wrong or interrupted. If you want the target's update to be atomic operation, or to record modification time, or have to prevent other types of errors, these reasons have made you do this.
4.6 Recursive Use Recursive Use Make is using the make command in makefile. This technique is decomposed into several subsystems in you, which is useful for each self-system with a Makefile. For example, there is a subdirectory 'Subdir' has its own makefile, I hope that Make can run in the directory, you can do this: Subsystem: CD Subdir; $ (Make) or Subsystem: $ (Make) -c subdir can look this; example To recursively using make4.6.1'make 'variables Make must use' make 'variables, not explicit MAKE commands: Subsystem: CD Subdir; $ (Make) The value of the variable is the name of the Make called. Use 'make' in the command: It changed `-t '(` --touch'), `-n '(` --just-print') and `-q '(` --question) 'The meaning of the option. Using the previous example, consider the 'make -t' command ('-t' option to mark the target as the latest but not running command), more '-t' option, will create a 'subsystem' file, actually hopeful The operation is running 'cd subdir; make -t'; however, this will execute the command, which does not match '-t'. This special function has made a desired work. When the command line contains variable 'make', option '-t', '- n' and '-Q' are not applicable. Regardless of these, the commands that do not perform commands are not executed, and the commands containing the 'make' variable will always be executed. The normal 'Makeflags' mechanism passes these logos to subkey so that the request for print commands is propagated into the subsystem.
4.6.2 Transfer Variables The variables in the Top-Level Make can be explicitly passed to the subkey through the environment. In sub-Make, these variables are defined by default, but do not reload the definitions in the subkey, unless the '-e' option is used. In order to transfer, or output variables, Make adds it to the environment variable when running commands; subkey can use environment variables to initialize variables. Unless explicitly required, Make only outputs a variable in the initial environment or the command line settings and the variable name consists of only letters, numbers, and underscores. Some shells cannot handle environment variables with other characters. Special variables 'shell', 'makeflags' always output, if the 'makefile' variable values, it will also be output. Make automatically outputs the variable defined by the command line via 'makeflags'. If you want to output a specific variable, use the 'export' instruction: Export Variable ... If you want to block the output variable, use 'UNEXPORT' instructions: Unexport Variable ... For your convenience, you can output it when defining variables: Export variable = Value and Variable = ValueExport Variable effect. If you want to output all the variables, use the 'Export' instruction itself. The variable 'makeevel' will change at the primary level at level 1, the value of this variable is a string of the number of nested layers. Top-level 'make' is, the value of the variable is '0'; the value of the subkey is '1' The value of the child Make is '2', and so on. The use of 'MakeElevel' is to test it in the conditional instructions, which writes Makefile that performs different time when recursive operation and direct runtime. hide
