Serial acquisition mode in the single-chip voltmeter ICL7135 Application author of the article: Article type Wangren Huang Yan still friends: design applications Article Joined: October 22, 2003 1: 3 Article Source: foreign electronic components
Abstract: The specific method of serial data acquisition for the A / D chip ICL7135 is introduced. At the same time, the configuration is simple, the programming is simple, and the characteristics of the single-chip resources are used, which gives the ICL7135 and the AT89C52 single-chip microcomputer into a voltage meter system. And software design methods.
Keywords: single-chip ADC voltage meter ICL7135
In commonly used A / D conversion chips (such as ADC0809, ICL7135, ICL7109, etc.), the ICL7135 is different from the remaining several, it is a four-bit double-integral A / D converter with high precision (accuracy is quite) At 14 binary numbers), low price, strong anti-interference ability. Typically, the designers are data using the microcontroller to acquire ICL7135 in parallel, which describes the data of ICL7135 with a single-chip serial manner to implement a single-chip voltage meter and a small intelligent instrument design.
1 ICL7135 serial work mode
1.1 ICL7135 measurement cycle
The measurement cycle of the ICL7135 includes the following four-phase (beat):
(1) Auto-Zero (Automatic zeroing) phase in this phase, internal IN and IN-input and pin are open, and connected to ANLG-COMMON inside, the reference capacitor is charged to the reference voltage, the system is connected to a closed loop And automatically charge the Autozero capacitor to compensate for the offset voltage of the buffer amplifier, integrator, and comparator. At this time, the automatic zeroing precision is limited by the system noise, with the total dispensing of the input-based, less than 10 μV.
(2) Singal-Integrate phase
In this phase, the automatic zero ring is opened, the internal IN and IN-input are connected to the external pin. Differential voltages between these inputs are integrated within a fixed time period. When the input signal is not inverted relative to the converter power supply, IN- can be directly connected to anJG-Common to output the correct common mode voltage. At the same time, on the basis of this completion, the polarity of the input signal will be recorded by the system.
(3) Deintegrate
The phase of the phase is used to complete the Deintegrate task. At this time, internal connections ANLG-COMMON, IN is connected to the previously charged reference capacitor, the polarity of the recorded input signal ensures that it is correct. Polar connection to the capacitor to make the integrator output polar zero. The time required to return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital reading and is determined by 1000 (VID / VREF). The fullness or maximum conversion value occurs when the VID is equal to twice the VREF. (4) Zero-Integrate (returning zero)
In-connection to ANLG-COMMON, the system is connected to a closed loop to return the integrator output to zero. Usually this phase requires 100 to 200 clock pulses, but 6200 pulses are required after the overrange converted.
1.2 ICL7135 timing chart
Figure 1 shows the ICL7135 timing chart when the VID is constant, as can be seen from Fig. 1: At the beginning of Signal-Integrate (ie, the signal integration), the BUSY signal line of the ICL7135 jumps high and remains high until de integrate. The point is collected from the end. In the event of a full range, the number of most pulse in this area is 30002. The pulse of the de Integrate phase reflects the result of the conversion. Figure 2 is a timing of ICL7135 when different VID values. As can be seen from Figure 2: For different analog inputs, the high level width of the BUSY signal of the ICL7135 is also different.
2 serial connection with the single chip system
When ICL7135 is connected to the single chip system, if the parallel acquisition method of ICL7135 is used, it is necessary to connect the BCD code data output line, but also to connect the bit drive signal output of BCD code data, which requires at least 9 I / O port lines. . Therefore, the system's connection is more troublesome and the programming is also very complicated.
The serial connection of the ICL7135 is to obtain measurement conversion results by a method of measuring the number of pulses. It can be seen from the timing analysis, and the number of pulses and conversion results have one correspondence between the DEINTEGRATE phase.
In fact, the pulser can be measured by a timer T0 (such as Atmel's 51 Series Single Chip AT89C52) (also using the timer T1). Since the CLK frequency used by the timer T0 is 1/12 of the system crystal resonant frequency. Therefore, the ALE signal of the single chip (AT89C52) can therefore be used as a pulse (CLK) input of ICL7135. But note that in software design programming, if the MOVX instruction does not appear in the instruction, the pulse frequency generated by the ALE terminal will be 1/6 of the crystal. At this point, the relationship between the frequency and the crystal rate of the microcontroller system can be found, and the relationship between the frequency input required for ICL7135 and the crystal rate of the microcontroller system.
In order to synchronize the ICL7135 required for the counting pulse of the timer T0, the BUSY signal of the ICL7135 can be connected to the P3.2 (INT0) pin of the AT89C52, and the Timer T0 is gated by 1 . The timer T0 is working will be controlled by the busy signal. As can be seen from the above timing, when the ICL7135 starts operating, ie, when the integration waveform is started, the timer T0 starts working, and the TH0, TL0 recorded by the timer T0 is recorded. There is a certain proportional relationship with the ICL7135 test pulse (at the beginning of the DEINTEGRATE phase in this area, the pulse of the DEINTEGRATE phase is referred to as the measurement pulse). Its system connection diagram is shown in Figure 3.
In this case, the clock used by the timer T0 and ICL7135 is not the same path. Therefore, some proportional relationship between the data recorded by the timer T0 should be found. A proportional relationship between the measurement pulses should be found. The proportional relationship is as follows:
FTIME = FOSC / 12
Fale = FOSC / 6
FREAL = FOSC / 24
FICL = Fale / N
Among them, FOSC is a system crystal frequency; ftime is the frequency used for timer; FALE is the frequency of the single-chip ALE output; FREAL is the measurement pulse frequency of ICL 7135; the FICL is the input frequency used by ICL7135, which can be obtained by DALE. N is a divided ratio, and n should be selected as 4. Fig. 4 The ratio relationship between the connection diagram of the ICL7135A / D converter and the system can be seen that the frequency used by the timer T0 of the AT98C 52 is twice the frequency of the measurement pulse frequency of the ICL 7135. Therefore, the number of pulses recorded in the timer T0 is also twice the measurement pulse of the ICL7135. In the figure, the division may be selected according to the requirements of the ICL7135 and the clock frequency of the microcontroller. Here, it is advocated to use quadrestriction so that the timer T0 will not overflow when counting the measured pulse. If 4 or more divided numbers are used, it is necessary to make improvements on the software. To get the number of measuring pulses, simply remove the pulse number recorded by the timer to 2. The number of pulses corresponding to the A / D conversion result is obtained, and the number of measurement pulses is applied minus 10001. These conversions are usually done by software, so it is very simple. The number of impulse modes can be obtained by the number of pulses corresponding to the A / D conversion result. It can be seen from the discussion of the serial way: Use this method to expand the port line without using the 8255 chip. It has the advantage that the port line is small, can save the hardware resources of the system, improve the anti-interference ability of the system, and do not add any extended port devices to reduce the cost of the system.
3 Voltage meter design based on single chip microcomputer system
3.1 Hardware of the system
Figure 4 shows a typical connection diagram of the ICL7135 and the microcontroller system in a single chip voltage meter system. In the figure, the crystal of the microcontroller system is 6MHz, and the ALE signal frequency of the microcontroller is 1 MHz; considers the system connection and the frequency range of the single-chip ALE signal frequency range, the author takes the four-point frequency of the ICL7135 of the ALE signal, that is, 125 kHz. The benefit of this is that the T0 timer does not overflow when counting the measured pulse.
3.2 Software design of the system
The program flow chart of the software design system of the ICL7135A / D to the single-chip connection circuit is shown in Figure 5. The software flow chart consists of three parts. Where the converter subroutine is called in the main program, the purpose is to do not occupy a long interrupt time. The T0 counter is set to the mode 1, the timing state, the gate control is set to "1". Therefore, the TMOD control word is set to "05H". Since the T0 counter is used by the crystal frequency of the system, the effect is equal to the setting of the count state.
4 Conclusion
The serial mode of the ICL7135 is very good in practice. Compared to parallelism, its prominent advantages are simple structures, simple procedures, and less resources, which can improve anti-interference ability, while improving the detection reliability of the instrument, and may not add any extended port devices The cost of the system is reduced.
