New system-level language model provides integrated design environment for SOC designers
New System-Level Language Landscape is an INTEGRATION Vista for Soc Designers
■ Synopsys Dave Kelf
As project complexity improvements, the latest system language aggregates can promote the surge in production capacity, and benefit from design companies in the electronic design automation (EDA) industry. SystemverIlog and Systemc Coexistence in the design process, you can bring significant actual benefits and economic results. SystemverILog and Systemc are still considered two environmental exclusive environments, and now you can work together and provide smooth and smooth systems for implementing design and verification methods. The experience in the real design process clearly shows that these two languages are not intertwined, but also a complementary relationship. Use two languages in the same environment, which will bring indeadity and significantly shorten the project cycle. Systemc and SystemverIlog have their own features in different design areas. The combination of two standards will provide designer to select a comprehensive locale for designers from the system specification and door circuit layout until design verification. This combination can be regarded as an important part of the transition trend of tools and languages, which is to support the demand for end users, not just for the purpose of the tool. Systemverilog Encomver, SYSTEMVERILOG combines modern design and verification environments in a language, thereby eliminating a large number of bottlenecks in the chip design process. By establishing Verilog, this language can use more different functions in existing Verilog-based processes, making designers to walk less during cognitive processes. By combining Verilog and C language, SYSTEMVERILOG is easy to use, familiar with people, and provides features that achieve concise design and automated test platforms. Moreover, since the SystemverIlog language is the extension set of Verilog, it is quite convenient to use in the existing environment. SYSTEMVERILOG 3.0 provides a powerful foundation for the hardware design team, making the model quickly generate and easy to correct. The latest version of SystemVerilog 3.1 also adds a critical verification function to create a modern test platform. Confidential Design and Verification Platform SystemverILog contains all Verilog sources, including the Verilog IEEE 1364 Committee added new features in 2001. First-class generation functions, simplified port processing, dynamic variables, and various other functions make Verilog used more straightforward. Systemverilog 3.0 contains rich Basic C programming features such as types and components. SYSTEMVERILOG 3.1 (introduced in 2003) The new version will increase the performance and other important functions for specific targets, so that Verilog users have comprehensive flexibility in programming, which is critical for verification and system modeling processing. important. SystemverILog 3.0 mainly improves RTL encoding in the design process, and the various dedicated features contained in the latest version can make more confidential to write integrated RTL code, reduce working hours and fault risks. In addition, after strengthening, the new interface component provides the ability to generate new coding fields, allowing more deepest extraction and links to the architectural environment, and greatly improves the transparency of the design, and the judgment function is also introduced on this level. In this way, the designer can add a specification element in the code to further improve the authentication automation of the sector level. (See Figure 1) Unified Verification Improve Work Efficiency If SystemverIlog 3.0 is intended to improve design efficiency, then the version 3.1 focuses on increasing the verification efficiency. SystemverIlog provides individual, consistent grammar and semantics for test platform development. This language contains rich judgment, which is necessary to develop a detailed specification for verification. The new version has a feature running environment and automated test generator, which provides a powerful trading layer test programming feature, which is suitable for system and design implementation. SystemverIlog can meet all validation needs through a separate, simple aggregation language.
Figure 1: SystemverILog Components Systemver and SystemCSystemc have been widely recognized in the design world due to its open state, thereby having a large number of powerful, interoperable SYSTEMC-based tools and technologies. The main advantage of SystemC is to use standard software language and add structural and systematic functions, handle hardware and software collaborative design and integration in the form of an open C extension language. SYSTEMC is being more increasingly used to generate virtual prototypes designed by the on-chip system (SOC). These virtual prototypes encoded by SystemC or SystemverIlog can be applied to the trading layer, allowing signal details to replace effective performance. Despite a large number of systematic characteristics that allow the use of trading layer design and analysis, Systemverilog is mainly used to implement design and verification. For engineers engaged in RTL-level design and verification, this language can significantly improve the design process through a variety of functions. However, for today's methods, only the requirements for pure RTL design are not enough. The use of embedded processors is growing rapidly, with the development of a complete engineering platform to solve the problem of special portrait. SystemverIlog contains a lot of functions that meet the requirements based on platform design, especially in this environment. Use of reusable intellectual property (IP). Using interface implementation of standard communication mechanism modeling, check the protocol compliant system judgment, by a one-to-one mapping programming performance of C / C to HDL, which makes the embedded environment for data and control transfer. Embedded system development needs to provide models to hardware designers and software professionals. The SYSTEMC design takes into account this problem and provides an effective mechanism for platform modeling. The C / C design model must be provided for hardware and software engineers, and hardware-based functions are necessary for efficient, high-efficiency hardware modeling. Treating this most effective way to subtractive environment is to allow these languages to coexist. The basic components of the platform are IPs that can be modeled by C or HDL derived languages, signals, or trading layers. This IP can take the form of design components starting by the architecture layer and then further refinered to the implementation. Verify assemblies can also take an IP form for generating protocol flows or other standard I / O in the system layer. These IP components include system verification requirements and use the corresponding bus function model to reuse other verification processes. Systemverilog is equipped with a private interface. Through these interfaces, the bus function interface can be encoded in a transparent manner of the system or the engineer. Since these interfaces contain the transitions of communication validity, C / C to HDL and the judgment function of the bus function encoding, thereby providing a complete mechanism for the smooth ways from architecture to implementation. In this way, users can use their own habits to process the model without having to enter another area. Focus on the use of models rather than the design language, which indicates that both SYSTEMVERILOG and SYSTEMC have their own location in modern electronic methods. Synopsys recognizes while providing support for Systemc and SystemverIlog for end users. Synopsys is the initiator that supports Systemc and has been committed to the promotion of language standardization processes through public OpenVera test platform languages. In order to make SYSTEMVERILOG 3.1 to make the above contribution, SystemverILOG includes all functions required to simplify the RTL design. The demand for balancing users with language has now proved that C language design not only has high production efficiency, but also a supplement to the Verilog process. The integration of SystemVerilog / SystemCC enables the software team to work with their own programming languages when cooperating with the efficient hardware design and verification process, making the entire method approach under the appropriate production level. Tools and IP vendors are supporting SYSTEM VerIlog.
